2018
DOI: 10.1109/jssc.2018.2871632
|View full text |Cite
|
Sign up to set email alerts
|

All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1

Citation Types

0
16
0

Year Published

2019
2019
2023
2023

Publication Types

Select...
5
4

Relationship

3
6

Authors

Journals

citations
Cited by 26 publications
(16 citation statements)
references
References 15 publications
0
16
0
Order By: Relevance
“…Reference [18] demonstrates a 0.5-V ADPLL with a DCO operating directly at 0.5 V. However, its TDC is supplied at 1 V by an internal doubler. An ADPLL in [19] runs its DCO at 0.23 V and a doubler at 0.35 V to power the voltage-sensitive TDC. Reference [20] demonstrates a DT-RX directly supplied at 0.275 V via an sw-cap-based voltage doubler.…”
Section: Circuit Implementationmentioning
confidence: 99%
“…Reference [18] demonstrates a 0.5-V ADPLL with a DCO operating directly at 0.5 V. However, its TDC is supplied at 1 V by an internal doubler. An ADPLL in [19] runs its DCO at 0.23 V and a doubler at 0.35 V to power the voltage-sensitive TDC. Reference [20] demonstrates a DT-RX directly supplied at 0.275 V via an sw-cap-based voltage doubler.…”
Section: Circuit Implementationmentioning
confidence: 99%
“…1, produce ULV supplies (<0.3 V) that are well below the threshold voltage (V th ) of even the most recent FinFET CMOS transistors, thus making it extremely challenging for circuit designers. On the other hand, all-digital PLLs (ADPLL) are well known for their friendliness to low supply voltages and immunity from supply perturbations [2]. The major part of power consumption in the whole ADPLL lies in a digitally controlled oscillator (DCO) [2], [3].…”
Section: Introductionmentioning
confidence: 99%
“…Open-loop modulation has recently gained popularity in ULP TXs due to its energy-saving feature by shutting down the all-digital phase locked loop (ADPLL) loop after quickly acquiring the channel center frequency [1], [6], [8]- [10]. Further improvements in substantially lowering of the DCO flicker noise help to bring the carrier frequency drift to well within the IoT specifications [6], [10]. Under the open-loop scenario, the conventional TX architectures can be simplified as a convenient arrangement of a separate oscillator (e.g., voltage controlled oscillator (VCO) or DCO) and a PA [see Fig.…”
Section: Introductionmentioning
confidence: 99%
“…The power-saving benefits of the open-loop modulation can be extended for quasi-open-loop modulation. An ADPLL for BLE in[10] features a mere 1-kHz loop bandwidth so that almost all of its digital circuitry can operate in subthreshold, resulting in the DCO consuming 70% of its 0.9-mW power budget.This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/…”
mentioning
confidence: 99%