We present a new analog-to-digital converter (ADC)-based architecture of a phase-tracking receiver (PT-RX) optimized for ultra-low-power (ULP) and ultra-low-voltage (ULV) operations for the Internet of Things (IoT). The RX employs a type-II loop configuration that offers improved stability compared with the previous type-I PT-RX solutions. In addition, the type-II loop is also very tolerant of long run-lengths of consecutive "1" or "0" symbol sequences. Fabricated in 28-nm CMOS, the prototype PT-RX targets Bluetooth low energy (BLE) standard consuming only 1.5 mW at a supply of ≤0.7 V. It maintains an adjacent-channel rejection (ACR) of ≥−11/3.5/17/27 dB at 0/±1/±2/±3 MHz offset and can tolerate out-of-band (OOB) blockers of minimum −21 dBm across 1.0-3.5 GHz while also offering a best-in-class figure of merit (FoM) of 181 dB, with a 1-Mb/s BLE sensitivity of −93 dBm. Index Terms-Bluetooth low energy (BLE), digitally controlled oscillator (DCO)-based receivers (RXs), discrete-time (DT) filter, Internet-of-Things (IoT), phase-tracking RXs (PT-RXs), successive-approximation-register (SAR)-analog-to-digital converter (ADC), ultra-low power (ULP), ultra-low voltage (ULV). I. INTRODUCTION T HE massive deployment of Internet-of-Things (IoT) applications calls for ultra-low-power (ULP) and ultralow-voltage (ULV) design techniques for system-on-chip (SoC) devices realized in nanoscale CMOS [1]-[4]. The RF receiver (RX) is a key IoT subsystem that takes a significant portion of the IoT's total power budget. In the industry, commercial RXs using Cartesian [i.e., in-phase/quadrature (I/Q)] topology [5], [6] aimed at Bluetooth low energy (BLE), a dominant standard in IoT devices, consume 5-10 mW. A more recent industry work [1], a superheterodyne discrete-time (DT) Cartesian RX, achieves the lowest power of 2.75 mW with a sensitivity of −95 dBm. However, it becomes more and more challenging to further reduce the power allocation for the RX,

This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringecapacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 µW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.

We present an architecture of a Bluetooth low energy (BLE)-compliant receiver which, for the first time ever, breaks the 1 mW barrier of power consumption. It is based on a type-II phase-tracking loop and addresses the mutual magnetic coupling between on-chip inductors of a digitally controller oscillator (DCO) and low-noise transconductance amplifier (LNTA), which causes RX performance degradation in the priorart implementations. An inverter-based inductor-free LNTA is employed instead. The resulting adjacent channel rejection (ACR) improves by 1.5/2.5 dB at 2/3 MHz offset. By further leveraging current-reuse and switched-capacitor circuitry, this RX achieves the best-in-class FoM of 183.2 dB with sensitivity of −93.2 dBm. Thanks to the single-channel topology, the proposed RX occupies tiny area of 0.48 mm 2 in 28-nm CMOS. Index Terms-Bluetooth low energy (BLE) receivers (RXs), digitally controlled oscillator (DCO)-based receivers, discretetime (DT) receivers, Internet-of-Things (IoT), phase-tracking RXs (PT-RXs), inverter-based RXs, current-reuse, ultra-low power (ULP), ultra-low voltage (ULV).

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