All-digital self-adaptive PVTA variation aware clock generation system for DFS

Abstract

An all-digital self-adaptive clock generation system capable of adapt the clock frequency to compensate the effects of PVTA variations on the IC propagation delay and satisfy an externally set propagation length condition is presented. The design uses timeto-digital converters (TDCs) to measure the propagation length and a variable length ring oscillator (VLRO) to synthesize the clock signal. The VLRO naturally adapts its frequency to the PVTA variations suffered by its logic gates while the TDCs are used to track these variations across the chip and modify the VLRO length in order to adapt the clock frequency to them. The system measurements, for a 45nm FPGA, show that it adapts the VLRO length, and therefore the clock frequency, to satisfy the propagation length condition. Measurements also prove the system capabilities to act as a dynamic frequency scaling clock source since the propagation length condition value act as a frequency selection input and a strong linear relation between the input value and the resultant clock period is present.

Delay variation compensation through error correction using razor

“…From these results, further improvements can be made such as the inclusion of self-adaptive PVT variation aware clocks [6] in generating the Razor flipflop clocks. Since on-chip memories were included in the system, consideration of memory datapath variability against PVT can also be performed.…”