VLSI Design, Automation and Test(VLSI-Dat) 2015
DOI: 10.1109/vlsi-dat.2015.7114514
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All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction

Abstract: In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength selfcalibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designe… Show more

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