Photovoltaic energy harvesting is an attractive method of developing battery-free systems for wireless sensors, biomedical electronics, and the internet of things (IoT). To obtain an energy-efficient system, low-power digital circuits operating in the near/sub-threshold region are widely used in such applications. Therefore, the design of a low-voltage buck converter, which converts the harvested energy to the regulated output is critical. Sub-1V buck converters have been implemented using a large inductor [1] to operate in a continuous conduction mode (CCM). Both CCM and discontinuous conduction mode (DCM) operation has been demonstrated in [2], using an analog zero current detection (ZCD) technique to extend the available output power range. However, the analog circuit limits the minimum output power to 50μW, and reduces the conversion efficiency under light load conditions. This paper presents a tri-mode digital buck converter for photovoltaic energy harvesting with a maximum conversion efficiency of 92%. The targeted input voltage (V IN ) is 0.55−0.65V so as to meet the maximum power point voltages of the photovoltaic cell. The output voltage (V OUT ) ranges from 0.35−0.5V, in order to power the near/sub-threshold CMOS digital circuits with high energy efficiency. By integrating pulse-width modulation (PWM), pulse-frequency modulation (PFM), and asynchronous mode (AM), together with digital self-tracking zero current detection (ST-ZCD), the tri-mode digital buck converter effectively scales down the minimum output power to 50nW, while achieving more than 70% efficiency from 400nW to 10mW. The digital ST-ZCD automatically tracks the off-time of the power transistor, thus reducing the PFM power budget of the analog ZCD. Compared with the analog approach, the digital method is more robust under low voltage operation and the quiescent current can be reduced in order to improve the efficiency under light load conditions.The system architecture of the photovoltaic energy-harvesting buck converter is shown in Fig 20.10.1. The operating mode is determined based on output loading, with PWM for a heavy load, PFM for a middle load, and AM for a light load. The all-digital phase-locked loop (ADPLL) is activated in the PWM mode to provide clock signals to the digital pulse-width-modulation (DPWM) controller and the on-chip switched-capacitor dc-dc converter, boosting the gate voltage swing of the power transistors and significantly reducing the conduction loss caused by the low V IN . In the PFM mode and AM on the other hand, the ADPLL is disabled so as to prevent high switching power and provides only a constant delay to the constant on-time pulse generator. Because the target input voltage is close to the threshold voltage (V TH ) in CMOS technology, digital approaches are employed to achieve low voltage operation and reliable design. All functional blocks are biased by V IN , which can be as low as 0.55V. By detecting the input voltage and then adjusting and compensating for the logic delay, the tri-mode digital buck c...

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