PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems

Wu, Peng; Kuo, Yi-Ping; Wu, Chung-Shiang; Chuang, Ching-Te; Chu, Yuan-Hua; Hwang, Wei

doi:10.1109/socc.2014.6948914

Cited by 7 publications

(2 citation statements)

References 4 publications

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“…[36] IEEE 1500 CTW [37] Error and fault Data path checkers [38] detection NoC/Bus CRC checkers [27] Memory ECC [39] Adaptation PLL control [40] Voltage regulator [41] Body biasing generator [42] Power gating [43] Clock gating [44] sensor data and physical actuator controls are read/delivered using the IJTAG network (shown as red arrows). In addition, Cluster DMs and the System DM communicates also using the IJTAG network.…”

Section: Using Ijtag Network For a Hierarchical And Cross-layer Execu...mentioning

confidence: 99%

DARS: An EDA Framework for Reliability and Functional Safety Management of System-on-Chips

Ibrahim

Kerkhoff

2019

2019 IEEE International Test Conference (ITC)

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Electronic design automation tools used for Design-For-Test infrastructure insertion have often relied on test standards (e.g. IEEE 1149.1, 1500 and 1687) as a structured methodology for IC test access, which consequently reduce the design cost for DFT. The IEEE 1687 standard introduces an efficient methodology for the off-chip access of the increasing number of embedded instruments that are used for test, debug and other purposes. A subset of these instruments is also used for Reliability and functional Safety (RaS) management, while accessing them via an on-chip manager. In this paper, we present a design automation framework for the RaS management of System-on-Chips using embedded instruments, by utilizing the IEEE 1687 standard as the key enabler of this automation. The framework enables the on-chip execution of cross-layer RaS procedures by the automatic generation of a dedicated design layer for the procedures execution. The framework utilizes the IEEE 1687-defined PDL language and the pattern retargeting process for enabling a programming model for developing the RaS procedures with no regard to the instruments access procedures and their physical locations, which consequently reduce the development time of RaS procedures and enable their scalability and reusability, and hence their automation.

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Section: Using Ijtag Network For a Hierarchical And Cross-layer Execu...mentioning

confidence: 99%

DARS: An EDA Framework for Reliability and Functional Safety Management of System-on-Chips

Ibrahim

Kerkhoff

2019

2019 IEEE International Test Conference (ITC)

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“…reduce consumption, systems with dynamic consumption management (DPM) are used (Benini et al, 2000). DPM is used to control the power supply by voltage variation (Benini et al, 2000;Wu et al, 2014;Srivastava et al, 1996) or processor clock speed control (Zhuo et al, 2020;Benini et al, 2000;Rizvandi et al, 2017).…”

Section: Introductionmentioning

confidence: 99%

Panalysis of the Efficiency of the VRS Algorithm in the Transmission of Weather Data

PRLINCEVIC¹,

MILIVOJEVIC²

2021

EPSTEM

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In the first part of this paper a Variable rate sampling, algorithm for prediction has been described. Variable rate sampling systems were used for reducing power demand, by reducing the number of sent samples. In the second part is performed an experiment where is tested algorithm for prediction of data for transmission and transmitted data. For the purpose of this analyze transmission and predictions are performed for temperatures, air pressure, wind speed, and visibility. Prediction on the side of the transmission is performed using three different extrapolations (mam, mab, and ng). At the receiving side reconstruction of the received signal is performed applying Linear, Cubic, Makima, and Spline extrapolations, built into Matlab. A simple reconstruction is also performed, using the last known value for prediction the next value (this prediction is in the paper named Step extrapolation). Objective quality measures SR (correlation coefficient of reducing the number of samples between a number of measured and transmitted samples), and MAE (mean absolute error between the measured and predicted values of temperatures, pressures and visibility values) were calculated. The results are presented in the table and graphically.

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Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications

Akram

Hwang

2017

Analog Integr Circ Sig Process

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PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems

Cited by 7 publications

References 4 publications

DARS: An EDA Framework for Reliability and Functional Safety Management of System-on-Chips

DARS: An EDA Framework for Reliability and Functional Safety Management of System-on-Chips

Panalysis of the Efficiency of the VRS Algorithm in the Transmission of Weather Data

Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications

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