All Verilog mixed-signal simulator with analog behavioral and noise models

Mayes, M.K.; Chin, S.W.

doi:10.1109/amicd.1996.569382

Cited by 14 publications

(2 citation statements)

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“…A further benefit of this Verilog technique is that the full delay estimated gate-level digital models can be simulated with first-order delay accurate analog functional cells. This avoids the zero time delay analog model problem of some behavioral approaches [4].…”

Section: Introductionmentioning

confidence: 99%

On behavioral modeling of a mixed-signal analog to digital converter

Wey

McGough²

2005

48th Midwest Symposium on Circuits and Systems, 2005.

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Section: Introductionmentioning

confidence: 99%

On behavioral modeling of a mixed-signal analog to digital converter

Wey

McGough²

2005

48th Midwest Symposium on Circuits and Systems, 2005.

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“…Other techniques have been proposed to model and simulate the noise generation. In [3] and [4] methodologies are proposed that use verilogHDL and analogHDL routines to count the switching transitions of a digital circuit and calculate the substrate noise using mathematical expressions. Because a mathematical expression is used for the generated substrate noise, rather than the real waveforms, these simulations can never result in an accurate prediction of generated substrate noise.…”

Section: Introductionmentioning

confidence: 99%

High-level simulation of substrate noise generation including power supply noise coupling

Heijningen

Badaroglu

Donnay

et al. 2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate noise generated by large digital circuits is however not feasible with existing circuit simulators and detailed substrate models due to the long simulation times and high memory requirements. We have developed a methodology to simulate this substrate noise generation at a higher level. Not only does this methodology take noise coupling from switching gates into account, but also noise coupling from the power supply is included. This paper describes this simulation methodology. In the paper it is shown that the high-level simulations correspond very well with SPICE simulations and that a large gain in simulation speed is obtained. This high-level simulation methodology makes it possible to predict substrate noise generation of large digital circuits in a very efficient way, early in the design flow of mixed-signal ASICs.

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