High-level simulation of substrate noise generation including power supply noise coupling

Abstract

Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate noise generated by large digital circuits is however not feasible with existing circuit simulators and detailed substrate models due to the long simulation times and high memory requirements. We have developed a methodology to simulate this substrate noise generation at a higher level. Not only does this methodology take noise coupling from switching gates into account, but also noise coupling from the power supply is included. This paper describes this simulation methodology. In the paper it is shown that the high-level simulations correspond very well with SPICE simulations and that a large gain in simulation speed is obtained. This high-level simulation methodology makes it possible to predict substrate noise generation of large digital circuits in a very efficient way, early in the design flow of mixed-signal ASICs.

Simulation of substrate coupling in mixed-signal IC's using an efficient and real-time macromodel

“…• Mathematical models [2] • Equivalent switching models [3] • SubWave Methodology [4] • Universitat Polit'ecnica de Catalunya Methodology [5] • Susbstrate Waveform Analysis (SWAN) Methodology [6] • Input independent macromodels [7] • ADAMIN [8] Because of figure and page limitation, the details of the above-macromodels aren't presented here. One can find the details of mentioned-macromodels in the relative references.…”

“…The macromodel will be the basis of a noise evaluation methodology similar to Refs. [4,5,6]. The proportional macromodels for each gate are combined for complete circuit macromodel.…”

“…For example, if the source is at gate, then this capacitance is the gate capacitance. The values of Zvdd, Zgnd and Zint are calculated based on process technology information and cell layout [5,6]. The key problem here is that the values of the Ceq and Req will be different depending on whether the gate is switching in static '0' or in static '1' state.…”

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

“…From the digital part, some work has been devoted to design low-switching-noise digital CMOS circuits [2,3,4] and to develop techniques to evaluate how noisy digital circuits are [5,6]. At the circuit level, supply and substrate currents are taken as a measure of the noise generation [5,6] while at the logic level, it is the switching activity density which has been taken as an adequate noise generation profile [5].…”

On the interaction of power distribution network with substrate

“…To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED'01, August 6-7, 2001 In the past, much effort has been placed on the extraction of accurate substrate models [5,[8][9][10][11][12][13]. A number of commercial solutions for extracting detailed substrate models are available [6][7][8].…”