2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC) 2020
DOI: 10.1109/nss/mic42677.2020.9507972
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ALTIROC 1, a 25 ps time resolution ASIC for the ATLAS High Granularity Timing Detector

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Cited by 8 publications
(4 citation statements)
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“…The power budget for these boards is at the level of a few tens of mA and cannot clearly be scaled up for too many channels. For example, ATLAS [ 33 ] and CMS [ 34 ] timing detectors will use dedicated fast pixelated electronics, whose power consumption is about 1 mW/channel, and there continue to be on-going efforts which are not in the scope of the present work. The logical path forward is to integrate the read-out electronics in the same sensor substrate, using CMOS processes, as already happens with MAPS.…”
Section: Discussionmentioning
confidence: 99%
“…The power budget for these boards is at the level of a few tens of mA and cannot clearly be scaled up for too many channels. For example, ATLAS [ 33 ] and CMS [ 34 ] timing detectors will use dedicated fast pixelated electronics, whose power consumption is about 1 mW/channel, and there continue to be on-going efforts which are not in the scope of the present work. The logical path forward is to integrate the read-out electronics in the same sensor substrate, using CMOS processes, as already happens with MAPS.…”
Section: Discussionmentioning
confidence: 99%
“…Both collaborations are developing new read-out ASICs for their respective timing layers: ALTIROC [30] designed in 130 nm CMOS technology by ATLAS and ETROC [31] in 65 nm CMS technology by CMS. ALTIROC and ETROC are the first attempts to develop large ASICs (about 2x2 cm 2 ) dedicated to reading LGAD sensors, aiming at a sensor-electronics combined single hit resolution below 50 ps.…”
Section: Standard Lgad and Ti-lgadmentioning
confidence: 99%
“…ALTIROC1 has been designed on a CMOS 130 nm process and achieves a 25 ps time resolution, with 25 channels per ASIC. Each channel integrates an RF preamplifier, followed by a high speed discriminator and two TDCs for Time-of-Arrival and Time-Over-Threshold measurements, as well as a local memory [27]. The TDC, designed by SLAC, is based on a Cycling Vernier Delay Line with a resolution of 20 ps and a maximum range of 2.5 ns (7 bits dynamic range).…”
Section: Asic Randdmentioning
confidence: 99%