Amplifier gain enhancement with positive feedback

Pude, M.; Mukund, P.R.; Singh, Prashant; Paradis, Ken; Burleson, J.

doi:10.1109/mwscas.2010.5548800

Cited by 10 publications

(7 citation statements)

References 7 publications

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“…Positive feedback has been discussed previously in other literature . This work is an extension of our prior work by measuring the effects of positive feedback on the frequency response of CMOS amplifiers. Positive feedback is analyzed in a generic manner so that it can be applied to any circuit topology meeting the described criteria with the addition of a small feedback factor.…”

Section: Introductionmentioning

confidence: 85%

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

Pude

Mukund

Burleson³

2013

Circuit Theory & Apps

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The use of positive feedback as a solution to intrinsic gain degradation in scaled CMOS technologies, such as 65 nm and below, is discussed in detail. Criteria for increasing gain while keeping the system stable are derived using a positive feedback amplifier model. These criteria are shown to provide significant gain enhancement in silicon. This work extends the previously reported DC gain analysis to include evaluation of additional effects of positive feedback as well an investigation of the frequency behavior using S-parameter measurements in silicon. These S-parameter measurements of fully differential positive feedback amplifiers designed in TSMC's 65 nm technology show gain enhancements of up to 26.7 dB at frequencies up to 8.5 GHz.

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Section: Introductionmentioning

confidence: 85%

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

Pude

Mukund

Burleson³

2013

Circuit Theory & Apps

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“…In the presence of high parasitic capacitance, the resonant drive circuit fails to drive the parallel-plate actuator over its entire gap, although it is able to extend the operation range beyond the conventional pull-in point. To enhance the inherent negative feedback of the resonant drive circuit, we exploit the gain enhancement technique of an op-amp implemented with a positive feedback loop [51][52][53].…”

Section: Resonant Drive Circuit With Enhanced Inherent Negative Feedbackmentioning

confidence: 99%

Low Voltage Electrostatic Actuation and Displacement Measurement Through Resonant Drive Circuit

Park

Abdel‐Rahman

2012

Volume 5: 6th International Conference on Micro- And Nanosystems; 17th Design for Manufacturing and the Life Cycle Conference

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Most electrostatic actuators fabricated by MEMS technology require high actuation voltage and suffer from the pull-in phenomenon that limits the operation range. We present an amplitude-modulated resonant drive circuit to drive electrostatic actuators at much lower supply voltage than that of conventional actuators to extend their operation range. Analytical and numerical models facilitate stability analysis of electrostatic actuators coupled with the resonant drive circuit. We study the impact of parasitic capacitance and the quality factor of the resonant drive circuit on the operation range of electrostatic actuators. Furthermore, we present a new method to measure the displacement of electrostatic actuators by sensing the phase delay of the actuation voltage with respect to the input voltage. This measurement method allows us to easily incorporate feedback control into existing electrostatic actuators without any modification to the actuator itself.

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“…A. Baschirotto et al [ 20 ], designed a front-end using a single-ended amplifier as CSA. The circuit works at high frequency and very low voltage; however, the disadvantages of that circuit are high power consumption and high equivalent noise charge (ENC) which worsen the radiation-hardened behavior of the circuit [ 9 , 19 , 25 , 28 , 29 ]; furthermore, the circuit was prone to more parallel noise generated by the passive feedback resistor. The main problem in designing nuclear spectroscopy very large scale integration (VLSI) readout front ends is the execution of low-noise and low-power CSA, which guarantees high particles flux with the lowest pulse pile-up.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, a good choice in the pulse shaping parameters is crucial for achieving good energy resolution and minimum pulse pile-up for high counting rates [ 11 , 30 , 31 ]. For high throughput experiments, short shaping time (

) reduces the pile-up effects and for an optimal design solution, the minimum

limits the charge collection process and increases the energy resolution accordingly [ 4 , 12 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 ]. Therefore, it is necessary to propose an optimal front-end circuit to avoid unnecessary power dissipation and heat in closely packed pixel arrays first avoid.…”

Section: Introductionmentioning

confidence: 99%

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Jérôme

Evariste

Bernard

et al. 2021

Sensors

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The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

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Amplifier gain enhancement with positive feedback

Cited by 10 publications

References 7 publications

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

Low Voltage Electrostatic Actuation and Displacement Measurement Through Resonant Drive Circuit

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

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