Amplitude and gain error influence on time error estimation algorithm for time interleaved A/D converter system

Elbornsson,; Gustafsson,; Eklund, Peter

doi:10.1109/icassp.2002.1005984

Cited by 7 publications

(10 citation statements)

References 2 publications

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“…We see that even for these strong mismatch errors and the strong timing jitter the calculated SINAD is, except for quantization and jitter uncertainties, identical to the simulated one. Moreover, even the approximate SINAD (21), where all error sources are separated, only slightly deviates from the simulation results.…”

Section: F Derivation Of the Expected Sinad For Individual Mismatch contrasting

confidence: 54%

“…Moreover, for the first time, we have introduced the concept of a meta TIADC, which allows us to consider the mutual influence of timing jitter and combined mismatch errors for an arbitrary number of channels (20). We have shown a way to separate the timing jitter power and the mismatch error power with (21). Furthermore, we have performed worst case analyses for individual errors.…”

Section: Discussionmentioning

confidence: 99%

“…Gain and offset mismatch compensation in oversampled ADCs is investigated in [19]. A time-domain identification method for timing mismatches, which utilizes statistical properties of signals with timing mismatches, is introduced in [20] and evaluated in [21] and [22]. Another possibility to improve the performance of a time-interleaved ADC is randomizing [23], [24].…”

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confidence: 99%

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The Impact of Combined Channel Mismatch Effects in Time-Interleaved ADCs

Vogel

2005

IEEE Trans. Instrum. Meas.

189

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Abstract-A time-interleaved multichannel analog-to-digital converter (ADC) achieves high sampling rates with the drawback of additional distortions caused by channel mismatches. In this paper, we consider the dependency of the signal-to-noise-and-distortion ratio (SINAD) on the combination of several different channel mismatch effects. By using either explicitly given mismatch parameters or given parameter distributions, we derive closed-form equations for calculating the explicit or the expected SINAD for an arbitrary number of channels. Furthermore, we extend the explicit SINAD by the impact of timing jitter. We clarify how channel mismatches interact and perform a worst case analysis of the explicit SINAD for individual mismatch errors. We also show that equations describing the expected SINAD of individual mismatch errors are special cases of our general formulation. We indicate how to use the expected SINAD for finding efficient optimization priorities and demonstrate the importance of worst case analyses.Index Terms-Analog-to-digital converter (ADC), channel mismatch, error analysis, signal-to-noise-and-distortion ratio (SINAD), time-interleaving, timing jitter.

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Section: F Derivation Of the Expected Sinad For Individual Mismatch contrasting

confidence: 54%

Section: Discussionmentioning

confidence: 99%

mentioning

confidence: 99%

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The Impact of Combined Channel Mismatch Effects in Time-Interleaved ADCs

Vogel

2005

IEEE Trans. Instrum. Meas.

189

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“…3. The offset mismatch and gain mismatch are primarily compensated to avoid the influence of offset and gain mismatches on sample-time error estimation and compensation [15]. The sample-time error compensation block consists of two functional blocks.…”

Section: Sample-time Error Compensation Using Cubic Spline Interpolationmentioning

confidence: 99%

Correction of Sample-Time Error for Time-Interleaved Sampling System Using Cubic Spline Interpolation

Qin¹,

Liu²,

Gao³

et al. 2014

Metrology and Measurement Systems

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Sample-time errors can greatly degrade the dynamic range of a time-interleaved sampling system. In this paper, a novel correction technique employing a cubic spline interpolation is proposed for inter-channel sample-time error compensation. The cubic spline interpolation compensation filter is developed in the form of a finiteimpulse response (FIR) filter structure. The correction method of the interpolation compensation filter coefficients is deduced. A 4GS/s two-channel, time-interleaved ADC prototype system has been implemented to evaluate the performance of the technique. The experimental results showed that the correction technique is effective to attenuate the spurious spurs and improve the dynamic performance of the system.

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“…There exist three main mismatch errors, including the gain mismatch error, the offset mismatch error and the time-skew error between the clock signals distributed to them. These errors will ultimately limit the system performance, causing the so-called pattern noises and significantly degrading the signal to noise and distortion ratio (SINAD) [14][15][16][17]. Detailed discussions about the mismatch errors can be found in Refs.…”

Section: Introductionmentioning

confidence: 99%

A new method of waveform digitization based on time-interleaved A/D conversion

Ye¹,

Liu²,

Feng³

et al. 2013

Chinese Phys. C

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Time interleaved analog-to-digital conversion (TIADC) based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limitation in hardware design and to implement the mismatch correction algorithm in real time, this paper proposes a fully parallel correction algorithm. A 12-bit 1-Gsps waveform digitizer with ENOB around 10.5 bit from 5 MHz to 200 MHz is implemented based on the real-time correction algorithm.

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Amplitude and gain error influence on time error estimation algorithm for time interleaved A/D converter system

Cited by 7 publications

References 2 publications

The Impact of Combined Channel Mismatch Effects in Time-Interleaved ADCs

The Impact of Combined Channel Mismatch Effects in Time-Interleaved ADCs

Correction of Sample-Time Error for Time-Interleaved Sampling System Using Cubic Spline Interpolation

A new method of waveform digitization based on time-interleaved A/D conversion

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