An 0.3-μm Si epitaxial base BiCMOS technology with 37-GHz f/sub max/ and 10-V BV/sub ceo/ for RF telecommunication

Nii, H.; Yoshino, C.; Yoshitomi, Sadayuki; Inoh, K.; Furuya, H.; Nakajima, H.; Sugaya, H.; Naruse, H.; Katsumata, Y.

doi:10.1109/16.753705

Cited by 13 publications

(8 citation statements)

References 9 publications

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“…5 shows the simulated Gummel characteristics and the common-emitter current-gain of a double poly-emitter npn bipolar transistor of a 0.3 µm BiCMOS process, where the geometry and doping information was taken from Ref. [12]. One observes an increase of the maximum gain by 25% due to the effect of ii.…”

Section: Application Examplesmentioning

confidence: 98%

Physical Model of Incomplete Ionization for Silicon Device Simulation

Schenk

Altermatt

Schmithüsen

2006

2006 International Conference on Simulation of Semiconductor Processes and Devices

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An empirical model of incomplete ionization (ii) in phosphorus-, arsenic-, and boron-doped crystalline silicon is derived from photoluminescence, conductance, and mobility measurements. It is found that up to 25% of phosphorus and boron atoms and up to 35% of arsenic atoms are non-ionized at room temperature near the Mott transition, whereas there is no significant amount of ii at dopant densities far above the Mott transition. Simplified equations of ii suitable for implementation in device simulators are exploited to study the effect of ii on the performance of bipolar and MOS devices. It is demonstrated that ii can increase the current gain of bipolar transistors by up to 25%.

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Section: Application Examplesmentioning

confidence: 98%

Physical Model of Incomplete Ionization for Silicon Device Simulation

Schenk

Altermatt

Schmithüsen

2006

2006 International Conference on Simulation of Semiconductor Processes and Devices

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“…Recently Nii et al [37] have analysed the published data on frequency and breakdown voltage of SiGe HBTs and have found that in general the HBTs which have high f max have low BV CEO . Supply voltages in analogue and mixed circuits are decreasing and therefore one might think that a very high value of BV CEO is not necessary.…”

Section: Transistors With High Bv Ceo and High F Maxmentioning

confidence: 99%

“…High values of BV CEO with high values of f max can be obtained by reducing parasitic capacitance and base resistance [37]. This can be accomplished by using an epitaxially grown base, with a flat impurity profile in the base, and optimizing the collector epilayer thickness.…”

Section: Transistors With High Bv Ceo and High F Maxmentioning

confidence: 99%

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SiGe HBT for application in BiCMOS technology: II. Design, technology and performance

Jain

Decoutere

Willander

et al. 2001

Semicond. Sci. Technol.

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SiGe technology has acquired great importance in recent years. Recent advances made in the SiGe HBT technology for analogue applications are discussed in this two-part review paper. Strain, stability, reliability, mobility of charge carriers, bandgap narrowing and effective density of states of SiGe layers have been discussed in part I. This paper (part II) is devoted to the HBTs: their design and performance. The two designs of the HBTs developed by IBM and by Daimler-Benz are discussed. Their relative merits and constraints imposed by the stability criterion on each design are described. The technology used for implementing the two designs is also described. The dc and ac characteristics and Ge profiles needed to optimize different figures of merit are discussed in detail. The parasitic barriers created by outdiffusion of B and also on operating the HBT at high current densities are explained. High injection barriers can be suppressed by a special design of the Ge profiles. Introduction of C in the base suppresses outdiffusion of B. HBTs with SiGeC base layers are discussed. Issues involved in simultaneous optimization of f T , f max and BV CEO are addressed. Values of f T , f max and BV CEO of high-performance HBTs are compiled and given in a table. The noise characteristics of the SiGe HBTs are far superior to those of III-V devices. Noise in SiGe HBTs is discussed in detail. Finally, a summary of selected circuits that have been fabricated using SiGe HBTs is given.

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“…More recently, it was reported on a 0.3 m Si epitaxial base BiCMOS technology where DT and ST were polysilicon and oxide filled, respectively, and STI-CMP was stopped on polysilicon on active area. 6 The slurry was not described further, only that it had a selectivity of oxide toward polysilicon of about ten. It has been reported that by adding nonionic surfactants, which adsorb on a polysilicon surface, the removal of polysilicon could be decreased and thereby increasing selectivity of oxide toward polysilicon.…”

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confidence: 99%

A Shallow and Deep Trench Isolation Process Module for RF BiCMOS

Forsberg

Johansson

Liu

et al. 2004

J. Electrochem. Soc.

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A shallow and deep trench isolation process module for high performance rf bipolar complementary metal-oxide-semiconductor ͑BiCMOS͒ is presented in detail. The shallow trench is etched prior to the deep trench, allowing the deep trench to be placed self-aligned to the shallow trench edge. By planarizing the polycrystalline silicon deep trench filling using chemical mechanical polishing ͑CMP͒ before etchback, the recess into deep trenches is decreased and polysilicon spacer formation at the active area edges is avoided. The poly CMP is stopped before all polysilicon in the active area is removed, to avoid polysilicon dishing and erosion of oxide on top of nitride on active area. Important issues arising during process development are discussed. Two different slurries were evaluated, which resulted in two different nonuniformities of polysilicon thickness. Nonuniformity transfers partially down to a range of recesses into the deep trenches, but the recesses were much smaller compared to the etchback only. Highdensity chemical vapor deposition was used for shallow trench filling and a direct shallow trench isolation-CMP process was developed. The feasibility of the process module was demonstrated using a 0.25 m, 200 mm bipolar double-poly rf process with optional SiGe epi base. Electrical results from completed transistors are presented to verify the function of the module.All nontrivial integrated electronics involve connecting isolated devices through specific electrical connection paths. The device isolation scheme is, therefore, one of the critical parts for integrated circuit processes. Many different schemes have been developed over the years. Parameters like minimum isolation spacing, surface planarity, defect density, process complexity, and electrical properties ͑dc and high frequency͒ influence the choice of a scheme for the particular application and process technology. Mesa isolation, junction isolation, and localized oxidation of silicon ͑LOCOS͒ are techniques in use. As feature sizes continue to decrease, there is a need to reduce shortcomings, such as low packing density, high leakage currents, and latch-up between devices, associated with older isolation technologies.In complementary metal-oxide-semiconductor ͑CMOS͒ technology, LOCOS has been replaced by shallow trench isolation ͑STI͒. 1,2 The lateral encroachment into the active area when using LOCOS, due to oxidation under the nitride at the edges, can be avoided by using STI. Thereby, the lateral control increases, tighter design rules can be applied, and parasitic capacitances are reduced. STI also offers a more planar surface and the possibility to increase the field oxide thickness.A complexity in high-performance rf bipolar complementary metal-oxide-semiconductor ͑BiCMOS͒ processes is the integration of STI with deep trench isolation ͑DTI͒. Deep trenches, usually with a depth larger than a couple of micrometers, are mainly used to isolate different devices and device groups ͑wells͒ in CMOS/ BiCMOS technology. The trenches are filled with oxide...

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An 0.3-μm Si epitaxial base BiCMOS technology with 37-GHz f/sub max/ and 10-V BV/sub ceo/ for RF telecommunication

Cited by 13 publications

References 9 publications

Physical Model of Incomplete Ionization for Silicon Device Simulation

Physical Model of Incomplete Ionization for Silicon Device Simulation

SiGe HBT for application in BiCMOS technology: II. Design, technology and performance

A Shallow and Deep Trench Isolation Process Module for RF BiCMOS

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