Proceedings of the IEEE 2012 Custom Integrated Circuits Conference 2012
DOI: 10.1109/cicc.2012.6330578
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An 8.5–11.5Gbps SONET transceiver with referenceless frequency acquisition

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Cited by 1 publication
(3 citation statements)
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“…Also, note that simulating all frequency detectors in 65nm CMOS at 10Gb/s (with the same gates) result in a power consumption of 6mW for the proposed FD and 29.5mW and 28.6mW for the FDs in [3] and [4], respectively. Since the details of the design in [6] and [7] are not available, they cannot be simulated. Also exact transistor count cannot be obtained.…”
Section: Fd On Fd Offmentioning
confidence: 99%
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“…Also, note that simulating all frequency detectors in 65nm CMOS at 10Gb/s (with the same gates) result in a power consumption of 6mW for the proposed FD and 29.5mW and 28.6mW for the FDs in [3] and [4], respectively. Since the details of the design in [6] and [7] are not available, they cannot be simulated. Also exact transistor count cannot be obtained.…”
Section: Fd On Fd Offmentioning
confidence: 99%
“…When frequency error is close to zero, the FD becomes inactive, and the PD takes full control of the VCO. Due to concurrent operation, the two loops can interfere with each other [5,6] and delay phase locking. In [6], the FD and PD loops are uncoupled, where the FD changes the VCO frequency by switching capacitors in and out of the tank.…”
Section: Introductionmentioning
confidence: 99%
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