An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC

Sarkar, Santanu; Banerjee, Swapna

doi:10.1109/isvlsi.2009.12

Cited by 19 publications

(7 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The digital part have D latch, and basic logic gates (AND, OR) connected to latch [1]. The input given to logic gate AND is combination of row and column decoder output with cascading inverter, which provide synchronization by delaying the input.…”

Section: Fig 2: Schematic Design Of Current Cellmentioning

confidence: 99%

“…Segmentation is combination of unary coding and binary weighted current steering DAC. Percentage of segmentation depends on number of bits used in unary coding in DAC [1]. In many research paper segmentation has done with the combination of binary weighted and unary coding, only changing the percentage of segmentation according to need of speed, power and bandwidth.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design and analysis of 8 bit fully segmented digital to analog converter

Baranwal

Singh

2015

2015 2nd International Conference on Recent Advances in Engineering &Amp; Computational Sciences (RAECS)

View full text Add to dashboard Cite

This paper presents design of an 8-bit 1.8V fully segmented digital to analog converter (DAC) using 180nm CMOS technology. DAC is an essential part of digital signal processor. Digital to analog converter is employed in processing of digital signals and providing analog output in the form of current or voltage for corresponding binary input. The differential non linearity of a DAC shows variation in output corresponding to 1LSB change at input that is accuracy of data conversion. To achieve low non linearity or more accurate data conversion a DAC is designed with unary coding or a fully segmented digital to analog converter with current steering technique. The INL and DNL achieved in this research work are 0.145LSB and 0.013LSB respectively. The power consumption is simulated as 99.67mW.

show abstract

Section: Fig 2: Schematic Design Of Current Cellmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design and analysis of 8 bit fully segmented digital to analog converter

Baranwal

Singh

2015

2015 2nd International Conference on Recent Advances in Engineering &Amp; Computational Sciences (RAECS)

View full text Add to dashboard Cite

show abstract

“…In [30], the paper proposed 8 bit DAC which the aim is to obtain optimal performance with small area. The circuit is implemented into 6 MSB and 2 LSB sequences.…”

Section: Figure 5 Dac Configurationmentioning

confidence: 99%

Low Power Designs of Current Steered DACs in CMOS Process: A Review

Mazlanna

Mazlan

Jalil

et al. 2015

ijeei

View full text Add to dashboard Cite

Low power design has become popular nowadays because ofdevelopment of improveddata converters with high resolution in CMOS process. Electronic device manufacturersare competing each other to produce devices that can extend battery life, have inexpensive packaging and cooling systems as well as reduce the size.The objective of this paper is to review various low power designs in digital to analog converters (DAC). The methods used to reduce the power consumption are presented in details. We focused the designs in the segmentation current steering DACs, as most of the low power designs illustarted in literatures are based on this architecture. From this review, we find that triple segmented architectureand spike free switching can reduce the power consumption effectively. This review paper can be a reference for the researchers and engineers to develop low power CMOS DACsfor various applications.

show abstract

“…The current mode DAC was completed by using binaryweighted architecture and thermometer-decoder, as shown in Figure 2. The ideal thermometer-decoder segmented architecture in [17] [18] was 60~70%. In other words, if an input was 10-bit, the ideal thermometer encoder would be 6-bit or 7-bit.…”

Section: Architecture Of the High Voltage Digital-to-analog Convmentioning

confidence: 99%

Design of high voltage digital-to-analog converter for electrical stimulator

Hsueh

Chen

2012

2012 IEEE Asia Pacific Conference on Circuits and Systems

View full text Add to dashboard Cite

In this study we proposed a 10-bit high voltage digital-to-analog converter (HV-DAC) for electrical stimulator. The HV-DAC was designed for maximum output current of 100mA and 50 V in TSMC 0.25-μm HV mixed signal based BCD 2.5/5/60V process. The proposed DAC has good linear output, and the simulation results showed that the maximum DNL and INL were -0.03LSB and -0.28LSB respectively, while the setting time was 23.11ns.

show abstract

An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC

Cited by 19 publications

References 7 publications

Design and analysis of 8 bit fully segmented digital to analog converter

Design and analysis of 8 bit fully segmented digital to analog converter

Low Power Designs of Current Steered DACs in CMOS Process: A Review

Design of high voltage digital-to-analog converter for electrical stimulator

Contact Info

Product

Resources

About