An 800Mhz cryptographic pairing processor in 65nm CMOS

Li, Yang; Han, Jianda; Wang, Shuai; Fang, Dabin; Zeng, Xiaoyang

doi:10.1109/ipec.2012.6522664

Cited by 7 publications

(3 citation statements)

References 4 publications

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“…[16,20] are the improved version of designs in Ref. [15,19], respectively. Therefore, we only compare the results with design in Ref.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…Besides theoretical optimisation, hardware acceleration is also an effective way to improve pairing performance. The hardware implementation of the optimal ate pairing over BN curves has been studied by several groups [13–22]. By invoking one F p multiplication, Fan [13] and Kammler [14] designed optimal ate pairing processors with low hardware resource consumption for the optimisation of F p and

{F}_{{p}^{2}}

operations.…”

Section: Introductionmentioning

confidence: 99%

“…By invoking one F p multiplication, Fan [13] and Kammler [14] designed optimal ate pairing processors with low hardware resource consumption for the optimisation of F p and

{F}_{{p}^{2}}

operations. To accelerate

{F}_{{p}^{2}}

operations, ( A + B )mod P based on Montgomery method was implemented by the processors proposed by Li [15] and Han [16]. Hao [17] and Bahadori [18] studied the parallelism of

{F}_{{p}^{2}}

in hardware.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A high‐performance processor for optimal ate pairing computation over Barreto–Naehrig curves

Xie

Wang

Zhang

et al. 2022

IET Circuits, Devices & Syst

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This paper presents a high-performance processor for optimal ate pairing on Barreto-Naehrig curves over 256-bit prime field at the 128-bit security level. The proposed design exploits parallelism and pipeline at different levels of the pairing algorithm, including the prime field operation, the second extension of the prime field F p 2 À � operation, and operations based on F p 2 . The proposed design needs 37,271 cycles to compute optimal ate pairings. The results of implementation on a 90 nm standard cell library show that the proposed design consumes 751k gates and can compute the respective pairings in 0.10 ms. This result is at least 60 percent better than related reports in terms of normalised area-time on ASIC. Moreover, the design is also implemented on Xilinx Virtex-6 platform, which consumes 25K Slices and 240 DSPs and takes 0.52 ms to calculate one optimal ate pairing operation.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…[16,20] are the improved version of designs in Ref. [15,19], respectively. Therefore, we only compare the results with design in Ref.…”

Section: Implementation Resultsmentioning

confidence: 99%

{F}_{{p}^{2}}

operations.…”

Section: Introductionmentioning

confidence: 99%

“…By invoking one F p multiplication, Fan [13] and Kammler [14] designed optimal ate pairing processors with low hardware resource consumption for the optimisation of F p and

{F}_{{p}^{2}}

operations. To accelerate

{F}_{{p}^{2}}

operations, ( A + B )mod P based on Montgomery method was implemented by the processors proposed by Li [15] and Han [16]. Hao [17] and Bahadori [18] studied the parallelism of