An a VLSI driving circuit for memristor-based STDP

Abstract

The main goal in realizing aVLSI (analog VLSI)\ud systems able to mimic functionalities of biological neural networks is pointed to the reproduction of realistic synapses. Indeed,\ud because of the relative high synapse/neuron ratio, especially in\ud the case of extremely dense networks (i.e., reproduction of a real\ud scenario), synapses represent a considerable limitation in terms\ud of waste of silicon area and power consumption as well. Thanks\ud to advancement made in the implementation of memristor, the\ud interest in bio-inspired neural network design has been renewed.\ud Memristors have tunable resistance which depends on its past\ud state; this is analogous to the operating mode of biological\ud synapses. In this paper, we present the circuit implementation of\ud a simple memristor-based neural network. Here, we propose a\ud driving circuit model that not requires specific shape input pulses\ud to change the memristor conductance (i.e., synaptic strength), but\ud it can be driven by arbitrary shaped input pulses. Moreover, this\ud prototype circuit offers the chance of emulating the standard\ud STDP behavior allowing “controlled” changes for the synaptic\ud weights. Some preliminary experimental results are reported to\ud validate the proposed driving circui

Towards Neuro-Inspired Electronic Oscillators Based on The Dynamical Relaying Mechanism

“…In this phase, we have generated the dynamical relay model with Orcad PSpice, consisting in three LIFL neurons connected with delay, using the implementation of the LIFL neuron presented in [23]. We have sized the circuit in order to obtain a period of 40 μs, in the driven synchrony regime.…”

“…The SNN that we implemented is based on the biologically plausible leaky integrate and fire with latency (LIFL) neuron model [18]- [22]. Firstly, we implemented the system equations in Matlab®; then, we have realized the schematic of such system in PSpice®, exploiting a circuit previously developed by our group [23], [24]. Finally, the model has been validated to verify whether 1) it observes the fundamental properties of the dynamical relaying mechanisms described in computational neuroscience studies, and 2) if the circuit implementation presents the same behaviour of the mathematical model.…”

Hardware design of LIF with Latency neuron model with memristive STDP synapses

“…In case of spiking neural networks composed of a large number of neurons, the very high number of synapses makes them the main source of power consumption. For this reason, the synapse driving circuit presented in [41] has been improved taking into account the specific characteristics of our application. The most significant changes are the following.…”

“…Fig.9. It represents the main source of power consumption is the circuit developed in [41]. In particular, Figure 11: (A) Simple simulated circuit composed of 3 neurons (N1, N2, N3) and 2 synapses (S1, S2).…”

“…Figure 12: Circuit for power reduction. Subfigure a), c) are the previous version presented in [41]. The other subfigure b), d) are the new ones proposed in this work.…”