An abrupt InP-GaInAs-InP DHBT

Elias, D.C.; Kraus, S.; Gavrilov, A.; Cohen, Shimon; Buadana, Nadav; Sidorov, V.; Ritter, D.

doi:10.1109/led.2004.840707

Cited by 12 publications

(6 citation statements)

References 7 publications

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“…The present results confirm the potential of abrupt InP/InGaAs/InP DHBTs [8]. The barrier between the base and the collector is drastically reduced, if not, eliminated by inserting a δ-doped n-type InP at the BC junction.…”

Section: Discussionsupporting

confidence: 85%

“…The total collector layer thickness is ∼104 nm. As shown in [8], thin highly doped layers are sufficiently effective to eliminate the energy barrier between the base and the collector of InP/GaInAs/InP DHBTs. The base layer has been doped to ∼5 × 10 19 cm −3 to minimize the base resistance and compositionally graded from the collector toward the emitter.…”

Section: Growth and Fabricationmentioning

confidence: 99%

“…To overcome the electron blocking across the BC heterojunction, several grading schemes have been reported in the literature [6], [7]. Recently, an attractive alternative to compositional grading based on the insertion of a doping layer at the BC junction has been reported [8]. From a manufacturing point of view, this structure presents a great potential.…”

Section: Introductionmentioning

confidence: 99%

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High-Speed Selector–Driver Using Abrupt Delta-Doped InP/InGaAs/InP DHBTs

Driad

Makon

Ritter

2011

IEEE Electron Device Lett.

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This letter reports the potential of an InP-based double-heterojunction bipolar transistor (DHBT) using a thin highly doped n + -InP layer inserted at the base-collector junction. Molecular-beam-epitaxy-grown abrupt pulse-doped InPInGaAs-InP DHBTs ensure very high current gains of ∼90, low saturation voltages of less than 1 V, and high cutoff frequencies of ∼350 GHz. Using this technology, a compact high-speed highvoltage multiplexer-driver integrated circuit (IC) suitable for high-speed signal processing and communication systems has been designed and fabricated. The IC has successfully been measured at 112 Gb/s with very clear eye openings of up to 2 V pp with a power consumption of 2 W.

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Section: Discussionsupporting

confidence: 85%

Section: Growth and Fabricationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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High-Speed Selector–Driver Using Abrupt Delta-Doped InP/InGaAs/InP DHBTs

Driad

Makon

Ritter

2011

IEEE Electron Device Lett.

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“…Bipolar transistors having similar structures were demonstrated that exhibit cutoff frequency in the range of ∼100 GHz [24], [25], though the high frequency operation of a transistor having a filament emitter is yet to be evaluated.…”

Section: Discussionmentioning

confidence: 99%

Thermometry of Filamentary RRAM Devices

Yalon

Sharma

Skowroński

et al. 2015

IEEE Trans. Electron Devices

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Since thermal effects play a major role in filamentary RRAM devices, we compare the two localized thermometry methods developed for such devices. One method is based on short-pulsed measurements and the other on the measurement of minority-carrier injection from the filament into a semiconductor electrode by thermionic emission. We carried out and compared the measurements on the same functional oxide layer. Both methods indicate that the filament temperature is at least ∼550 K during device operation. Furthermore, comparison between the measured thermal resistance and the thermal simulations of both techniques shows that under the conditions of low forming current compliance (∼10 μA), the filament dimensions are below ∼5 nm. We show that the thermionic emission method is useful for high-resistance (>100 k ) devices operating at low-power conditions (<10 μW), whereas the pulsed thermometry is more suitable for lower resistance devices (<500 k ) operated above 1 μW. The average thermal resistance measured by the pulse technique decreases with applied power. Our simulations indicate that the expansion of the heated zone surrounding the filament can explain the observed reduction in thermal resistance with applied power. The underlying physics of the two methods is discussed.

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“…However, the complicated grading schemes required to reduce the current blocking conduction band discontinuity at the base/collector junction of the type-I DHBT undermine these advantages as the structures are vertically scaled to the dimensions required to achieve state-of-the-art values. The grading schemes required for type-I DHBTs often implement InGaAs spacers [2] or quaternary grading layers [3]; such transition layers are typically 40 to 60 nm thick, and present a limit to vertically scaling the device using collector thicknesses less than 70 nm, though an abrupt type-I design which uses a thin heavily InP layer at the base collector junction to minimize the energy barrier has also been demonstrated at low current densities [4].…”

Section: Introductionmentioning

confidence: 99%

Graded base type-II InP/GaAsSb DHBT with f/sub T/=475 GHz

Snodgrass

Hafez

et al. 2006

IEEE Electron Device Lett.

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The first demonstration of a Type-II InP/GaAsSb double heterojunction bipolar transistor (DHBT) with a compositionally graded InGaAsSb to GaAsSb base layer is presented. A device with a 0.4 6 m 2 emitter dimensions achieves peak of 475 GHz ( MAX = 265 GHz) with current density at peak exceeding 12 mA/ m 2 . The structure consists of a 25-nm InGaAsSb/GaAsSb graded base layer and 65-nm InP collector grown by MBE with breakdown voltage 4 V which demonstrates the vertical scaling versus breakdown advantage over type-I DHBTs.

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An abrupt InP-GaInAs-InP DHBT

Cited by 12 publications

References 7 publications

High-Speed Selector–Driver Using Abrupt Delta-Doped InP/InGaAs/InP DHBTs

High-Speed Selector–Driver Using Abrupt Delta-Doped InP/InGaAs/InP DHBTs

Thermometry of Filamentary RRAM Devices

Graded base type-II InP/GaAsSb DHBT with f/sub T/=475 GHz

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