Transistor designs based on using mixed -L valleys for electron transport are proposed to overcome the density of states bottleneck while maintaining high injection velocities. Using a self-consistent top-of-the-barrier transport model, improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb, and Ge-on-insulator-based singlegate thin-body n-channel metal-oxide-semiconductor field-effect transistors. All the proposed designs successively begin to outperform strained-Si-on-insulator and InAs-on-insulator (InAs-OI) in terms of ON-state currents as the effective oxide thickness is reduced below 0.7 nm. InAs-OI still exhibits the lowest intrinsic delay (τ ) due to its single valley.

The ALICE experiment will require some 1200 Readout Chips for the construction of the Silicon Pixel Detector [1] and it has been estimated that approximately 3000 units will require testing. This paper describes the system that was developed for this task.

We report on the performance of abrupt InP-GaInAs-InP double heterojunction bipolar transistors (DHBTs) with a thin heavily doped n-type InP layer at the base-collector interface. The energy barrier between the base and the collector was fully eliminated by a 4-nm-thick silicon doped layer with = 3 10 19 cm 3 . The obtainedand MAX values at a current density of 1 mA/ m 2 are comparable to the values reported for DHBTs with a grade layer between the base and the collector.

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