An accurate closed-expression model for FinFETs parasitic resistance

Pereira, A. S. N.; Giacomini, Renato

doi:10.1016/j.microrel.2015.01.006

Cited by 2 publications

(1 citation statement)

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“…At low field, the resistance of the channel can be characterized by the carrier mobility µ, which has been extensively measured and calculated in a variety of silicon structures (bulk, 3 films 4-12 and wires [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27] ). There is much less literature on the contact resistances, [28][29][30][31][32][33][34][35][36][37][38][39] even though they have become a major bottleneck for device performances. Most models for the contact resistances are based on driftdiffusion equations needing carrier mobilities as input, which might not be well characterized in the very inhomogeneous source/drain extensions.…”

Section: Introductionmentioning

confidence: 99%

Contact resistances in trigate and FinFET devices in a non-equilibrium Green's functions approach

Bourdet

Pelloux-Prayer

et al. 2016

Journal of Applied Physics

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We compute the contact resistances R c in trigate and FinFET devices with widths and heights in the 4 to 24 nm range using a Non-Equilibrium Green's Functions approach. Electron-phonon, surface roughness and Coulomb scattering are taken into account. We show that R c represents a significant part of the total resistance of devices with sub-30 nm gate lengths. The analysis of the quasi-Fermi level profile reveals that the spacers between the heavily doped source/drain and the gate are major contributors to the contact resistance. The conductance is indeed limited by the poor electrostatic control over the carrier density under the spacers. We then disentangle the ballistic and diffusive components of R c , and analyze the impact of different design parameters (cross section and doping profile in the contacts) on the electrical performances of the devices. The contact resistance and variability rapidly increase when the cross sectional area of the channel goes below 50 nm 2 . We also highlight the role of the charges trapped at the interface between silicon and the spacer material.

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