Analysis of the source/drain parasitic resistance and capacitance depending on geometry of FinFET

Pathak, Jay; Darji, Anand D.

doi:10.1109/prime.2015.7251394

Cited by 7 publications

(5 citation statements)

References 8 publications

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“…For example, the grid capacitance can have a significant influence on the inherent delay of the device. The S/D parasitic capacitance, which may be due to the top of the S/D region to the top of the gate or the top of the S/D region to the gate side wall, has a significant effect on the performance of devices, as well as the overall parasitic capacitance [1,2]. It depends on the geometry of the finFET as well as the material.…”

Section: Finfet Transistormentioning

confidence: 99%

The parasitic capacitance considerations of metal interconnects in sub 10 nm era

2024

J. Phys.: Conf. Ser.

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With the development of the integrated circuit industry and semiconductor technology, we have entered the sub-10 nanometers era, which means the distance between adjacent components in a device is less than 10 nm. This is a situation where the parasitic capacitance of metal interconnects must be considered. Parasitic capacitance can act as a significant influence in different ways on disparate devices. Fin field-effect transistors and microelectromechanical systems are typical devices and deserve further detailed explanation on their parasitic capacitance. There are many ways to reduce parasitic capacitance and its attendant effects, including using materials with low dielectric constants and optimizing the structure of the layout. Some others are newly brought out in recent years due to advanced industrial technology and new materials, including carbon nanotubes, oxide-free spacer layers, and tunneling hybrid technology. All these methods are of great significance and practicability to producing and applying semiconductor devices and structures. Knowing more about this expertise about parasitic capacitance can help us better understand its nature and specialties.

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Section: Finfet Transistormentioning

confidence: 99%

The parasitic capacitance considerations of metal interconnects in sub 10 nm era

2024

J. Phys.: Conf. Ser.

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“…The impact of parasitic resistance (also named access resistance) components on the performance degradation of scaled FinFET devices has been analyzed in recent years. [1][2][3][4][5][6][7] The parasitic resistance is typically composed of all resistive components that are not gate-controlled, namely the contact resistance (R cont ) at the interface between the metallic local interconnect and the source/drain (S/D) epi, and the S/D epi resistance itself (R epi ). In typical Si-channel p-FinFET devices, we have identified the presence of an additional interface resistance (R int ) component at the heterojunction between SiGe:B S/D epi and Si-channel.…”

Section: Introductionmentioning

confidence: 99%

Predictive and prospective calibrated TCAD to improve device performances in sub-20 nm gate length p-FinFETs

Eyben,

De Keersgieter,

Matagne

et al. 2024

Jpn. J. Appl. Phys.

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In this paper we present an extended analysis of the impact of SiGe p-epi source/drain engineering on sub-20nm gate length p-FinFETs performance for the N7 technology node. Different Ge concentrations and profiles (graded vs. non-graded) are evaluated making use of properly calibrated drift-diffusion TCAD simulations. Calibration of simulations is based on advanced metrology and on Monte-Carlo simulations such that the resulting simulated ID-VG (in LIN and SAT regimes) matches the one measured on device. The calibrated TCAD simulator is then used to understand the limited performances of the device and to propose new source/drain epi architectures with graded and increased Ge content. A new p-FinFET design is fabricated and tested, confirming a boost in ON-current and a reduction of the parasitic resistance. Prospective TCAD work is also presented suggesting possible future improvements on p-epi source/drain and on local interconnect contacts.

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“…The impact of parasitic resistance and capacitance on the overall device performance is becoming more prominent as technology is scaled down. 3) Compared with a single-fin FinFET, a multifin FinFET composed of more than one fin can improve device drain current while parasitic RC effects are expected to change according to the number of fins and the difference in fringe field in such a structure. Also, to facilitate the formation of fine patterns in such advanced technologies, dummy patterns are generally added in the layouts, which has become a necessity to reduce loading and edge effects during fabrication processes.…”

Section: Introductionmentioning

confidence: 99%

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Huang¹,

Meng²,

King³

et al. 2017

Jpn. J. Appl. Phys.

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A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns as well as multifin structures are analyzed and modeled in detailed. By incorporating parasitic resistance and capacitance extracted by both measurement and simulation, the static and dynamic performance characteristics of standard six transistor static random-access memory (6T-SRAM) cells are comprehensively evaluated as an example of parasitic RC effects in this investigation.

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Analysis of the source/drain parasitic resistance and capacitance depending on geometry of FinFET

Cited by 7 publications

References 8 publications

The parasitic capacitance considerations of metal interconnects in sub 10 nm era

The parasitic capacitance considerations of metal interconnects in sub 10 nm era

Predictive and prospective calibrated TCAD to improve device performances in sub-20 nm gate length p-FinFETs

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

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