An Accurate EEGNet-based Motor-Imagery Brain–Computer Interface for Low-Power Edge Computing

Abstract

This paper presents an accurate and robust embedded motor-imagery brain-computer interface (MI-BCI). The proposed novel model, based on EEGNet [1], matches the requirements of memory footprint and computational resources of low-power microcontroller units (MCUs), such as the ARM Cortex-M family. Furthermore, the paper presents a set of methods, including temporal downsampling, channel selection, and narrowing of the classification window, to further scale down the model to relax memory requirements with negligible accuracy degradation. Experimental results on the Physionet EEG Motor Movement/Imagery Dataset show that standard EEGNet achieves 82.43%, 75.07%, and 65.07% classification accuracy on 2-, 3-, and 4-class MI tasks in global validation, outperforming the stateof-the-art (SoA) convolutional neural network (CNN) by 2.05%, 5.25%, and 6.49%. Our novel method further scales down the standard EEGNet at a negligible accuracy loss of 0.31% with 7.6× memory footprint reduction and a small accuracy loss of 2.51% with 15× reduction. The scaled models are deployed on a commercial Cortex-M4F MCU taking 101 ms and consuming 4.28 mJ per inference for operating the smallest model, and on a Cortex-M7 with 44 ms and 18.1 mJ per inference for the mediumsized model, enabling a fully autonomous, wearable, and accurate low-power BCI.

EEG-TCNet: An Accurate Temporal Convolutional Network for Embedded Motor-Imagery Brain–Machine Interfaces

“…Interestingly, variable EEG-TCNET requires, in general, a smaller number of temporal filters F 1 and filter size K E than EEGNet. The temporal filters pose the most restrictive limitations in terms of computational complexity and memory footprint since the temporal convolution requires the vast majority of MACs and memory to store the resulting feature maps [19]. Therefore, variable EEG-TCNET has more potential to be embedded on a resource-limited device.…”

“…TPCT's overall memory footprint is 8.304 MB, and thus far beyond the on-chip memory capacity available in an ARM M7 processor. Its compute effort of 1.73 GMACs would take approximately 50 s/inference-17× below real-time when requiring a new classification at least every 3 s-where we refer to the throughput of 34.45 MMAC/s of an ARM M7 processor [19]. In comparison, the proposed EEG-TCNet has a memory footprint of 400 kB, and its compute effort of 6.8 MMACs would take approximately 197 ms. EEG-TCNET and variable EEG-TCNET are the best candidates for an embedded implementation; both parameter count and inference cost are kept reasonable while still achieving very high accuracy scores.…”

“…However, accurate networks such as the TPCT model have 7.78 M trainable parameters and require 1.73 billion multiply-accumulate (MAC) operations per inference, which is out of reach of a typical low-power MCU with few MB of Flash and few hundreds of kB of RAM [18]. Alternatively, more compact models such as EEGNet with 2.5 k parameters and 13 MMACs can come to the rescue and have been successfully implemented on MCUs [19], [20]. Still, they come at the cost of significantly lower classification accuracy of 72.40%.…”

Q-EEGNet: an Energy-Efficient 8-bit Quantized Parallel EEGNet Implementation for Edge Motor-Imagery Brain-Machine Interfaces

“…In [14], EEGNET was applied to the Physionet Motor Movement/Imagery Dataset, achieving SoA accuracy. The model was quantized and ported to an ARM Cortex-M7 using CUBE.AI, i.e., the X-CUBE-AI expansion package of STM32CubeMX.…”

“…Nevertheless, both Cortex-M and RISC-V based MCU platforms are tightly constrained both in memory and compute resources, which forced other embedded solutions to tailor and scale down EEGNET for the target system resulting in lower classification accuracy [14]. To address this challenge, we present Q-EEGNET, an adapted and quantized EEGNET [7] with algorithmic and implementation optimizations to execute BMI inference on resource-limited edge devices.…”