An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS

Zhang, Feifei; Chen, Peng; Walling, Jeffrey S.; Zhu, Anding; Staszewski, Robert Bogdan

doi:10.1109/tcsi.2021.3059368

Cited by 6 publications

(2 citation statements)

References 25 publications

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“…The digital pattern is re-sampled on-chip to the input clock rate (i.e., f c /9), which results in spectral images at this offset frequency from the f c carrier. Though not implemented in this prototype, spectral images can be further mitigated using additional digital interpolation or analog linear interpolation [36].…”

Section: Dynamic Measurementsmentioning

confidence: 99%

A mm-Wave Switched-Capacitor RFDAC

Nguyen

Walling

Zhu

et al. 2022

IEEE J. Solid-State Circuits

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This article proposes an interleaving switchedcapacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) operation. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edgecombining-based frequency-tripling delay-locked loop (DLL) in the clock generation network. The clock tripling is performed in each slice of the switched-capacitor PA (SCPA), which allows yet another 3× frequency reduction for the global clock distribution. Finally, a new layout structure accounts for transmission-line (TL) effects, due to the large physical size of the passive capacitor array. Implemented in 22-nm FD-SOI, the prototype achieves P out > 21 dBm, drain efficiency >36%, and system efficiency >22% while operating in the Ka-band at 28 GHz. Modulation at 2.4 Gb/s results in 3.3% EVM and 30.8-dBc adjacent channel leakage ratio (ACLR).

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Section: Dynamic Measurementsmentioning

confidence: 99%

A mm-Wave Switched-Capacitor RFDAC

Nguyen

Walling

Zhu

et al. 2022

IEEE J. Solid-State Circuits

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“…A VOIDING analog signal processing in transmitters for wireless communications results in benefits such as decreased power consumption and good technology scaling. Therefore, polar [1]- [5] and IQ [6]- [9] digital-intensive wireless transmitter (TX) architectures, as well as novel hybrid approaches such as multiphase [10]- [13], outphasing [14], triphasing [15], or hybrid IQ-polar [16] are becoming a popular choice for today's and future wireless TX architectures. The major challenge of TX architectures is the up-conversion of the baseband (BB) signal to a specific radio-frequency (RF) band, in ideal case without any unwanted spectral components, with high power efficiency supporting wideband single carrier and carrier-aggregated signals.…”

Section: Introductionmentioning

confidence: 99%

A Systematic Solution for the Problem of Spectral Degradation in Multiphase TX Architectures

Hamidović

Preyler

Preissl

et al. 2022

IEEE Trans. Circuits Syst. II

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With ever more stringent requirements of cellular standards it is an ongoing challenge to find the optimal RF transmitter architecture. In recent years, the multiphase transmitter (MP TX) architecture has been introduced as a promising candidate. It features high power efficiency and avoids phase modulation which is critical for upconversion of ultra-wideband signals. In this paper, the problem of unwanted spectral emission, inherent in MP TX architectures, is compensated by a proper data delay. Such an approach is considered for the first time in the multiphase architecture and achieves a spectral improvement of up to 38 dB in adjacent channels and 24 dB at the receiver (RX) duplex distance for a new radio (NR) signal with 20 MHz bandwidth. With the proposed solution the MP TX architecture becomes a highly competitive candidate for wideband signals such as LTE, LTE-CA or NR signals. In addition, a detailed and efficient implementation of the digital front-end (DFE) for the MP TX architecture including the proposed data delay is presented.

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Data‐driven Buck converter model identification method with missing outputs

Hou,

Zhang,

Wang

et al. 2024

IET Control Theory & Appl

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A data‐driven Buck converter model identification method is proposed to deal with missing (incomplete) outputs, which is robust to the data length and percentage of missing data. A nuclear norm based convex optimization problem instead of linear interpolation, to guarantee the recovered missing data satisfying the potential model structured low‐rank character, is constructed to estimate missing outputs. The alternating direction method of multiplier strategy is used to solve the nuclear norm based convex optimization problem. In this way, the high‐quality missing data can be estimated, even for short data length and high percentage of missing data. Based on the recovered data, the subspace identification method provides accurate estimates of the structure and parameter of the Buck converter synchronously. By applying the proposed method to a Buck converter, experimental results demonstrate its effectiveness.

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An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS

Cited by 6 publications

References 25 publications

A mm-Wave Switched-Capacitor RFDAC

A mm-Wave Switched-Capacitor RFDAC

A Systematic Solution for the Problem of Spectral Degradation in Multiphase TX Architectures

Data‐driven Buck converter model identification method with missing outputs

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