An AES crypto chip using a high-speed parallel pipelined architecture

Yoo, Seong-Moo; Kotturi, D.; Pan, Wei; Blizzard, John

doi:10.1016/j.micpro.2004.12.001

Cited by 63 publications

(25 citation statements)

References 15 publications

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“…There are a number of studies [17,18,19] that have focused on the performance improvement of this algorithm by using parallelization of its execution.…”

Section: Performance Improvementmentioning

confidence: 99%

Algorithm Aes - Structure, Transformations and Performance

Damjanović¹

2017

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Today' s cryptographic algorithms are designed in a way that they combine m athem atical theory and practice o f computer science in order to improve resistance to cryptanalysis. Cryptographic algorithms are designed around the binary data form at keeping in mind the presumption o f hardening possibility o f cracking the algorithm. One o f the algorithms whose resistance to cryptanalysis during the past 16 years is extensively tested algorithm AES. The Advanced Encryption Standard (AES) is the first cryptographic standard aroused as the result o f public competition established by U.S. National Institute o f Standards and Technology (NIST). AES has emerged as restriction on winner o f this com petition, called Rijndael algorithm on the block size o f 128 bits. From the moment o f its acceptance o f the standard in

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“…There are a number of studies [17,18,19] that have focused on the performance improvement of this algorithm by using parallelization of its execution.…”

Section: Performance Improvementmentioning

confidence: 99%

Algorithm Aes - Structure, Transformations and Performance

Damjanović¹

2017

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“…The different steps (Yoo, Kotturi, Pan, & Blizzard, 2005) in encryption part are explained with the help of the following Figure 1.…”

Section: Encryption Partmentioning

confidence: 99%

A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

Rahimunnisa

Karthigaikumar

Kirubavathy

et al. 2013

International Journal of Electronics

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A new architecture for encrypting and decrypting the confidential data using Advanced Encryption Standard algorithm is presented in this article. This structure combines the folded structure with parallel architecture to increase the throughput. The whole architecture achieved high throughput with less power. The proposed architecture is implemented in 0.13-µm Complementary metal-oxide-semiconductor (CMOS) technology. The proposed structure is compared with different existing structures, and from the result it is proved that the proposed structure gives higher throughput and less power compared to existing works.

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“…In addition, [19] employed loop unrolling, inner-round, and outer-round pipelining techniques with an optimum number of pipeline stages. In [39], authors presented a hardware efficient design for AES using a high-speed parallel pipelined architecture. Moreover, an efficient inter-round and intra-round pipeline design are employed to achieve high throughput.…”

Section: Introductionmentioning

confidence: 99%