An algorithmic error-resilient scheme for robust LDPC decoding

Abstract

To fit into multiple communication standards, flexible Low-Density Parity-Check (LDPC) decoding is desirable to be implemented in a chip multiprocessor (CMP) system. However, reliability issues, such as soft errors and timing errors, are severer in future advanced CMP systems when CMOS technology scale. Therefore, enhancing error resilience for a CMP system becomes an important design issue. In this paper, we propose a design methodology to achieve a robust LDPC decoding based on algorithmic error-resilient method. We firstly analyze the performance degradation caused by the soft errors which occur in the computing units (check node units and bit node units), and then explore the inherent error-tolerant characteristic of LDPC decoding algorithm. In our proposed method, we exploit some characteristic distribution or behavior in the operations of the LDPC decoding algorithm to validate the computing results. The experimental results show that the proposed algorithmic error resilience can approach the errorfree decoder while facing high injected soft-error rate of 10 -3 in computing units, but with only 6.07% computational overhead. To the best of our knowledge, this is the first discussion about the LDPC decoding algorithm in terms of soft errors in computing units.

Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories

“…There are many works on fault tolerant design for LDPC decoders, but most of them are for the protection against SEUs on the user memories. For example, [13] introduced time redundancy in the computing nodes, where the voting of multiple computations is applied to improve the reliability of the computing node. Differently, [14] proposed to apply Hamming codes to selectively protect the sign bit of the intermediate results, so that the reliability of the decoders can be improved with low overhead.…”