An all-ASIC implementation of a low bit-rate video codec

Fujiwara, Hiroshi; Liou, M.L.; Sun, Ming–Ting; Yang, K.-M.; Maruyama, Masashi; Shomura, Kazuyoshi; Ohyama, Kunio

doi:10.1109/76.143412

Cited by 47 publications

(9 citation statements)

References 11 publications

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“…However, the functionality is limited by the built-in instructions and architecture of the processors. With the pure hardware design, all the modules of a multimedia system are constructed with hardware circuits [8]. The hardware is used for a special-purpose multimedia system to exploit the maximal parallelism and to achieve the best performance simultaneously.…”

Section: Introductionmentioning

confidence: 99%

A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining

Wang

Peng

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

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We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.

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Section: Introductionmentioning

confidence: 99%

A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining

Wang

Peng

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

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“…To improve the perceptual visual quality, a postprocessor should be properly designed to remove these artifacts. Generally, the computational complexity of the postprocessing takes about 30%-50% of the total computational power in the decoder [6], [7]. Therefore, it is desirable to develop more efficient postprocessing algorithms to effectively remove the blocky effect.…”

Section: Introductionmentioning

confidence: 99%

“…In order to simplify the computation, however, the smooth block classification can be directly performed in the DCT-domain. In [18], the standard deviation is approximated as (7) where denotes the number of nonzero DCT coefficients. Thus, the block can be easily detected as a smooth block for or as a nonsmooth block for , where is a selected threshold.…”

Section: Introductionmentioning

confidence: 99%

Adaptive postprocessors with DCT-based block classifications

Liu

Yang

2003

IEEE Trans. Circuits Syst. Video Technol.

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In this paper, an adaptive postprocessor figured with discrete cosine transform (DCT)-based block classification to effectively remove the so-called blocky effect from compressed video sequences is proposed. The proposed DCT-based detection algorithms for both intraframes and interframes require much lower computation complexity than the spatial-domain approaches. In order to preserve the edge information, the adaptive postprocessor is also designed with a DCT-based edge detection mechanism such that a one-dimensional median filter can be adaptively adjusted to match with the edge orientation. Simulation results show that the proposed DCT-based detection algorithms accurately classifies smooth, edge, or nonsmooth blocks to help the adaptive postprocessor to effectively remove the blocky effect and sharply preserve the edge information.Index Terms-Adaptive median filter, transform coding, video coding, video signal processing.

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“…Since video processing algorithms are highly computationally intensive, they Rave been implemented by an embedded hardware rather than software [2], As the processing power of general-purpose processor increases, real-time video processing applications tend to be implemented based on software design nlowadays. However, this could not be the complete solution to fulfill the real-time requirement.…”

Section: I[ntroductionmentioning

confidence: 99%

Efficient hardware-software co-implementation of H.263 video codec

Kim

Jang²,

Lee³

et al.

1998 IEEE Second Workshop on Multimedia Signal Processing (Cat. No.98EX175)

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In this paper, an H.263 video codec is implemented by adopting the eoncept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed and flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and memory control. The other portion of the H.263 video codec and other parts of the H.324 system like G.723, H.223, and lH.245 are implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an architecture for a hierarchical mtotion estimator using correlation of neighboring motion vectors is suggested to reduce the chip size. Software optimization techniques are also explored using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD) obtained from the motion estimator. I[NTRODUCTIONThe coding of digital video sequences has drawn increasing attention over the last few years. Recently, H.263 his been adopted as the ITU standard [I], and is intended for videoconference, vidcophone, surveillance camera, and other low bit rate applications.Since video processing algorithms are highly computationally intensive, they Rave been implemented by an embedded hardware rather than software [2], As the processing power of general-purpose processor increases, real-time video processing applications tend to be implemented based on software design nlowadays. However, this could not be the complete solution to fulfill the real-time requirement. Consequently paralliel processing and multimedia instruction set extensions are generally adopted [:1,4].However, there exists a trade-oFf between the hardware and software in terms of iimplementatiorn. Hardware implementation is generally better than software iinplementation in processing speed and power consumption. In contrast, software can give a more flexible design solution and also be more suitable for various video applications.In order to fully use the advantages of both software and hardware, each module of the H.263 video codec is studied do determine a proper way of hardware-software partitioning. 'This paper describes which module can be appropriate to software implementation and investigates a software optimization

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An all-ASIC implementation of a low bit-rate video codec

Cited by 47 publications

References 11 publications

A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining

A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining

Adaptive postprocessors with DCT-based block classifications

Efficient hardware-software co-implementation of H.263 video codec

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