An all-digital delay-locked loop for high-speed memory interface applications

In this paper, we present a cell-based delay-locked loop (DLL) with an enhanced continuous tracking range. The main contribution is a novel delay line architecture called ping-pong delay line, making it highly resilient to process and temperature variation. In such a DLL design, two cell-based delay lines are incorporated in a way that they exchange their role of command dynamically like in a ping-pong game, and therefore the joint ping-pong delay line can react to severe environmental changes over a very wide range without disruption to the system's operation. The post-layout simulation using a 90-nm complimentary metal-oxide silicon (CMOS) process technology has demonstrated its advantages. A DLL using such a feature can operate reliably even under an extremely hostile environment when the supply voltage drops from 1 to 0.9 V within a timeframe of 4us.INDEX TERMS Cell-based DLL, delay line, ping-pong, segment jumping.

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An all-digital delay-locked loop for high-speed memory interface applications

Cited by 9 publications

References 10 publications

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing

Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines

A Ping-Pong Methodology for Boosting the Resilience of Cell-Based Delay-Locked Loop

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