An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

Isci, Canturk; Buyuktosunoglu, Alper; Chen, C.-Y.; Bose, Pradip; Martonosi, Margaret

doi:10.1109/micro.2006.8

Cited by 502 publications

(355 citation statements)

References 27 publications

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“…The reason is that the power related to the memory -which is the main component stressed by these benchmarks-can be easily modeled using just two states. This is because such component is less affected by the DVFS state changes 10 . Figure 7 shows the PAAEs of all the TD C related models against the BU DVFS 3 one for the LMBENCH suite, the most generic one.…”

Section: Accuracymentioning

confidence: 99%

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Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Bertran

González

Martorell

et al. 2012

The Computer Journal

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Counter-based power models have attracted the interest of researchers because they became a quick approach to know the insights of power consumption. Moreover, they allow to overpass the limitations of measurement devices. In this paper, we compare different Top-down and Bottom-up Counter-based modeling methods. We present a qualitative and quantitative evaluation of their properties. In addition, we study how to extend them to support the currently ubiquitous Dynamic Voltage and Frequency Scaling (DVFS) mechanism. We propose a simple method to generate DVFS agnostic power models from the DVFS specific models. The proposed method is applicable to models generated using any methodology and allows the reduction of the modeling time without affecting the fundamental properties of the models. The study is performed on an 18 DVFS states Intel R Core TM 2 platform using the SPECcpu2006, NAS and LMBENCH benchmark suites. In our testbed, a 6x reduction on the modeling time only increments 1 percentage point on average the error in the predictions.

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Section: Accuracymentioning

confidence: 99%

“…For instance, Dynamic Voltage and Frequency Scaling (DVFS) [8] allows to select the operating frequency of each core, thus, it permits to control the overall power consumption. This has been shown to be a powerful technology, and many proposals use it to implement power-aware policies such as power capping or power envelopes [9,10,11,12].…”

Section: Introductionmentioning

confidence: 99%

Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Bertran

González

Martorell

et al. 2012

The Computer Journal

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“…Sanchez and Kozyrakis, for example, show that fine-grained shared-cache cache partitioning is feasible in a large-scale CMP system [36], yielding greatly improved utilization. Similarly, multiple poweroriented studies [6,15,23] show that fine-grained, per-core DVFS regulation can greatly improve a CMP's energy efficiency. Intel has recently deployed a low-cost, fully-integrated voltage regulator in Haswell [19], and other researchers are making significant advances in supporting per-core DVFS [21,38].…”

Section: Motivation Of Our Approachmentioning

confidence: 99%

“…Cache and off-chip band-width are mostly related to the length of the memory phase: a larger L2 allocation will lower the cache miss rate, while more memory bandwidth will mitigate the penalty of cache misses. At the same time, a higher power budget allocation will allow a core to run at a higher frequency, and thus the compute phase will be scaled down proportionally [6,28].…”

Section: Utility Modelmentioning

confidence: 99%

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XChange: A market-based approach to scalable dynamic multi-resource allocation in multicore architectures

Wang

Martínez

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Efficiently allocating shared on-chip resources across cores is critical to optimize execution in chip multiprocessors (CMPs). Techniques proposed in the literature often rely on global, centralized mechanisms that seek to maximize system throughput. Global optimization may hurt scalability: as more cores are integrated on a die, the search space grows exponentially, making it harder to achieve optimal or even acceptable operating points at run-time without incurring significant overheads.In this paper, we propose XChange, a novel CMP resource allocation mechanism that delivers scalable high throughput and fairness. Through XChange, the CMP functions as a market, where each shared resource is assigned a price which changes over time, and each core seeks to maximize its own utility, by bidding for these shared resources. Because each core works largely independently, the resource allocation becomes a scalable, mostly distributed decision-making process. In addition, by distributing the resources proportionally to the bids, the system avoids unfairness, treating each core in an unbiased manner.Our evaluation shows that, using detailed simulations of a 64-core CMP configuration running a variety of multiprogrammed workloads, the proposed XChange mechanism improves system throughput (weighted speedup) by about 21% on average, and fairness (harmonic speedup) by about 24% on average, compared with equal-share on-chip cache and power distribution. On both metrics, that is at least about twice as much improvement over equal-share as a state-ofthe-art centralized allocation scheme. Furthermore, our results show that XChange is significantly more scalable than the state-of-the-art centralized allocation scheme we compare against.

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