An analytical drain current model for GS GAA MOSFET including interfacial traps

Abstract

It's widely recognized that Gate-All-Around (GAA) MOSFETs are considered among the most probable choices to continue CMOS performance boost beyond the conventional scaling frontiers. Such device offers the best controllability of short-channel effects claimed to be the predominant factor limiting how far the downscaling can be achieved. However, the lack of analytic compact models for degraded drain current can easily be notified in literature. Therefore, in this work we investigate the immunity of GAA MOSFET against the hotcarrier-induced degradation effect after considering the stepfunction approximation for interface charge distribution. The importance of including a high-k layer into the device architecture is also studied; the damaged device model presented in this work provides a simple and accurate approach for simulating the circuit behavior after hot-carrier damage.

Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

“…Recent research work done on JL-CSG MOSFET suggests it as a promising candidate to suppress SCEs [13][14][15]. Although, the JL-CSG MOSFET is a viable candidate for replacing the conventional bulk MOSFET, the hot carrier induced degradation still persists as a serious device reliability issue [16]. Reliability for any device is an important parameter along with optimum device performance [17].…”