An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures

Abstract

As capacity of the field-programmable gate arrays (FPGAs) continues to increase, power dissipated in the logic and routing resources has become a critical concern for FPGA architects. Recent studies have shown that static power is fast approaching the dynamic power in submicron devices. In this article, we propose an analytical model for relating homogeneous island-style-based FPGA architecture to static power. Current FPGA power models are tightly coupled with CAD tools. Our CAD-independent model captures the static power for a given FPGA architecture based on estimates of routing and logic resource utilizations from a pre-technology mapped netlist. We observe an average correlation ratio (C-Ratio) of 95% and a minimum absolute percentage error (MAPE) rate of 15% with respect to the experimental results generated by the Versatile Placement Routing (VPR) tool over the MCNC benchmarks. Our model offers application engineers and FPGA architects the capability to evaluate the impact of their design choices on static power without having to go through CAD-intensive investigations.

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

“…More recently, analytical approach models area, delay and power, allowing both static and dynamic power evaluation during design exploration [66], [67]. This allows designers to explore the impact of FPGA architecture parameters, including the number of logic cells and the associated switch boxes, wire lengths, and clock frequency [68].…”

“…This allows designers to explore the impact of FPGA architecture parameters, including the number of logic cells and the associated switch boxes, wire lengths, and clock frequency [68]. For instance, the authors in [66] improved the Poon's model [65] accuracy by integrating the width (W ) and length (L) of wires, delivering a static energy model that takes into account logic and routing architecture parameters.…”