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Intrusion detection is prominently important for civil and military applications in wireless sensor networks (WSNs). To date, related works address the problem by assuming a straight‐line intrusion path and a Boolean sensing model. However, a straight‐line intrusion path is often not the case in reality, and the Boolean sensing model cannot resemble a real‐world sensor precisely. Results based on these assumptions are therefore not applicable with desirable accuracy in practice. In view of this, we propose a novel sine‐curve mobility model that can simulate different intrusion paths by adjusting its features (amplitude, frequency, and phase) and can be integrated into the random WSN model for intrusion detection analysis. It can also be applied to different sensor models and makes influencing factors tractable. With the model, we examine the effects of different intrusion paths on the intrusion detection probability in a random WSN, considering both Boolean and realistic Elfes sensing models. Further, we investigate the interplays between network settings and intruder's mobility patterns and identify the benefits and side effects of the model theoretically and experimentally. Simulation outcomes are shown to match well with the theoretical results, validating the modeling, analysis, and conclusions. Copyright © 2011 John Wiley & Sons, Ltd.

As capacity of the field-programmable gate arrays (FPGAs) continues to increase, power dissipated in the logic and routing resources has become a critical concern for FPGA architects. Recent studies have shown that static power is fast approaching the dynamic power in submicron devices. In this article, we propose an analytical model for relating homogeneous island-style-based FPGA architecture to static power. Current FPGA power models are tightly coupled with CAD tools. Our CAD-independent model captures the static power for a given FPGA architecture based on estimates of routing and logic resource utilizations from a pre-technology mapped netlist. We observe an average correlation ratio (C-Ratio) of 95% and a minimum absolute percentage error (MAPE) rate of 15% with respect to the experimental results generated by the Versatile Placement Routing (VPR) tool over the MCNC benchmarks. Our model offers application engineers and FPGA architects the capability to evaluate the impact of their design choices on static power without having to go through CAD-intensive investigations.

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