An architecture design for anti-jamming circuit with low power and low area cost in high-precision GNSS receiver chip

Abstract

In this paper we propose an architecture of the anti-jamming circuit in high precision GNSS receiver chip base on the frequency-time domain solution, at most, the jamming signals of 12 frequency points can be detected and eliminated at the same time. In addition, an jamming detection strategy based on short-long time FFT is proposed and a circuit of FFT engine with low cost is designed to reduce the area and dynamic power of the GNSS receiver chip. Finally, we complete the VLSI design by using 55 nm digital process, the circuit area is 0.082 mm 2 , the average dynamic power is 0.943 mW. The implementation results prove the effectiveness of the proposed anti-jamming circuit.

Position and time deception based on satellite navigation technology and experimental verification

“…However, due to the weakness of satellite navigation signal and the disclosure of data format, the receiver is vulnerable to jamming and spoofing [7][8][9][10]. In order to improve the antiinterference performance of the receiver, many researchers have given solutions by different technical means, such as adding array antenna [11], integrated circuit design [12], and et.al [13]. Compared with the jamming effect that making the receiver unable to work, spoofing can make the receiver output wrong positioning and timing results, which is more threatening and harmful [14][15][16][17].…”

Dual-function slot antenna integrated with solar cells for the 1.575-GHz band

“…Many RF circuits have been studied and designed for global navigation satellite systems [1,2,3,4,5,6,7,8]. As the antenna plays an important role in the RF systems, many different types of antenna have been investigated and reported at 1.575 GHz including planar inverted-F antenna (PIFA) [9], U-shaped [10] and meshed [11] patch, spiral [12], substrate-integrated-waveguide [13] and monopole [14] antennas.…”