An Asynchronous Energy-Efficient CNN Accelerator with Reconfigurable Architecture

Chen, Weijia; Wu, Hui; Wei, Shaojun; He, Anping; Chen, Hong

doi:10.1109/asscc.2018.8579304

Cited by 14 publications

(5 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Data reuse is considered when PE is designed. The PE has three pipeline stages: data is loaded in the first stage, in the second stage the multiplication and truncation are accomplished, and the input data will be stored temporarily in the third stage [15].…”

Section: Case Studymentioning

confidence: 99%

A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools

Zhang

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

The "event-driven" feature of asynchronous circuits enables the circuits to work when and where needed, making it a good alternative to design low-power circuits. However, asynchronous circuits are not widely adopted as a consequence of the lack of support by conventional EDA tools. In this paper, we propose a novel design flow to implement the Click-based asynchronous bundled-data circuits efficiently down to mask layout with conventional EDA tools. To ensure timing correctness, we put forward an adaptive delay matching (ADM) method and perform accurate static timing analysis for the circuits. Compared with other asynchronous toolsets, the proposed design flow is more efficient and convenient to implement asynchronous circuits. An asynchronous convolution neural network accelerator is implemented in TSMC 180nm and 65nm CMOS process respectively to verify the proposed design flow. The silicon test results show that the asynchronous accelerator has 30% less power in computing array than the synchronous one in TSMC 65nm CMOS process, and the energy efficiency of the asynchronous and synchronous accelerators are 1.539 TOPS/W and 1.37 TOPS/W respectively. The energy efficiency of the asynchronous accelerator in TSMC 180nm CMOS process is 133 GOPS/W.

show abstract

Section: Case Studymentioning

confidence: 99%

A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools

Zhang

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Recently, an asynchronous reconfigurable SNN accelerator, known as ARSNN [9] , has been implemented based on the Link-Joint templates [10] ; an asynchronous Address-Event Representation (AER) arbitrating circuit supporting neuromorphic hardware with analog neurons was designed [11] ; and an asynchronous design scheme for a spiking Convolutional Neural Network (CNN) named ASIE [12] was proposed. In addition, reconfigurable asynchronous CNN accelerator chips [13,14] have been fabricated with a higher power efficiency than synchronous CNN chips.…”

Section: Introductionmentioning

confidence: 99%

Investigation of asynchronous pipeline circuits based on bundled-data encoding: Implementation styles, behavioral modeling, and timing analysis

Zhou

2022

Tsinghua Sci. Technol.

View full text Add to dashboard Cite

As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance.In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding, spanning different handshake signaling protocols such as 2-phase (micropipeline, Mousetrap, and Click), 4-phase (simple, semi-decoupled, and fully-decoupled), and single-track (GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.

show abstract

“…Many studies on CNN acceleration have adopted field-programmable gate arrays (FPGAs) as hardware platforms for evaluating performance because FPGAs have the advantages of reasonably high performance, rapid development, and reconfigurability, using software tools [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29]. They also have built-in complex computational units, such as digital signal processing (DSP) blocks for implementing large-scale arithmetic operations with maximum performance [30].…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based Convolutional Neural Network Accelerator with Resource-Optimized Approximate Multiply-Accumulate Unit

Cho

Kim

2021

Electronics

View full text Add to dashboard Cite

Convolutional neural networks (CNNs) are widely used in modern applications for their versatility and high classification accuracy. Field-programmable gate arrays (FPGAs) are considered to be suitable platforms for CNNs based on their high performance, rapid development, and reconfigurability. Although many studies have proposed methods for implementing high-performance CNN accelerators on FPGAs using optimized data types and algorithm transformations, accelerators can be optimized further by investigating more efficient uses of FPGA resources. In this paper, we propose an FPGA-based CNN accelerator using multiple approximate accumulation units based on a fixed-point data type. We implemented the LeNet-5 CNN architecture, which performs classification of handwritten digits using the MNIST handwritten digit dataset. The proposed accelerator was implemented, using a high-level synthesis tool on a Xilinx FPGA. The proposed accelerator applies an optimized fixed-point data type and loop parallelization to improve performance. Approximate operation units are implemented using FPGA logic resources instead of high-precision digital signal processing (DSP) blocks, which are inefficient for low-precision data. Our accelerator model achieves 66% less memory usage and approximately 50% reduced network latency, compared to a floating point design and its resource utilization is optimized to use 78% fewer DSP blocks, compared to general fixed-point designs.

show abstract

An Asynchronous Energy-Efficient CNN Accelerator with Reconfigurable Architecture

Cited by 14 publications

References 9 publications

A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools

A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools

Investigation of asynchronous pipeline circuits based on bundled-data encoding: Implementation styles, behavioral modeling, and timing analysis

FPGA-Based Convolutional Neural Network Accelerator with Resource-Optimized Approximate Multiply-Accumulate Unit

Contact Info

Product

Resources

About