An asynchronous instruction length decoder

Stevens, Kenneth S.; Rotem, S.; Ginosar, Ran; Beerel, Peter A.; Myers, Chris J.; Yun, K.Y.; Koi, R.; Dike, C.; Roncken, Marly

doi:10.1109/4.902762

Cited by 59 publications

(40 citation statements)

References 21 publications

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“…Analogous to RHBD's shortfalls in power and area penalties, asynchronous logic design is more complex when compared to the synchronous commercial standard and carries a potential area penalty. Perhaps the best-reported comparison of power, performance, and area impact of applying asynchronous design to a large commercial circuit, such as the Asynchronous Pentium Front End, can be found in [9]. Recent advances in automating the asynchronous design process have made the idea more attractive, resulting in new commercial offerings.…”

Section: Asynchronous Circuit Design Methodologymentioning

confidence: 99%

Radiation Hardening by Design of Asynchronous Logic for Hostile Environments

Barnhart

Vladimirova

Sweeting

et al. 2009

IEEE J. Solid-State Circuits

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Abstract-A wide range of emerging applications is driving the development of wireless sensor node technology towards a monolithic system-on-a-chip implementation. Of particular interest are hostile environment scenarios where radiation and thermal extremes exist. Radiation hardening by design has been recognized for over a decade as an alternative open-source circuit design approach to mitigate a spectrum of radiation effects, but has significant power and area penalties. Similarly, asynchronous logic design offers potential power savings and performance improvements, with a tradeoff in design complexity and a lesser area penalty. These side effects have prevented wider acceptance of both design approaches. A case study supporting the development of monolithic system-on-a-chip wireless sensor nodes is presented. Synchronous, hardened, and asynchronous/hardened implementations of a textbook microprocessor in 0.35 m austriamicrosystems SiGe BiCMOS technology are compared. The synergy of this novel asynchronous/hardened design approach is confirmed by simulation and hardware results.Index Terms-Asynchronous logic, environmental tolerance, radiation hardening by design, system-on-a-chip.

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Section: Asynchronous Circuit Design Methodologymentioning

confidence: 99%

Radiation Hardening by Design of Asynchronous Logic for Hostile Environments

Barnhart

Vladimirova

Sweeting

et al. 2009

IEEE J. Solid-State Circuits

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“…The POD/POC (pod → poc 0 ≺ poc 1 ) representation enables more efficient search and verification algorithms to be developed which greatly enhances the ability to combine timing with optimization, physical placement, and validation design tools [17]. This approach alters the way in which timing is represented by designers and CAD tools, and has been shown to provide significant power-performance advantages in some circuit designs [18], [20].…”

Section: Formal Timing and Verificationmentioning

confidence: 99%

“…Due to these factors the International Technology Roadmap for Semiconductors predicts that 20% of designs will be driven by handshake clocking in 2012, rising to 40% by 2020 [16]. Example designs that employ such methods have shown substantial improvements in power, performance, and latency [23], [18].…”

Section: Introductionmentioning

confidence: 99%

Characterization of Asynchronous Templates for Integration into Clocked CAD Flows

Stevens

Vij

2009

2009 15th IEEE Symposium on Asynchronous Circuits and Systems

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Abstract-Asynchronous circuit design can result in substantial benefits of reduced power, improved performance, and high modularity. However, asynchronous design styles are largely incompatible with clocked CAD, which has prevented wide-scale adoption. The key incompatibility is timing. Thus most commercial work relies on custom CAD or untimed delay-insensitive design methodologies. This paper proposes a new methodology, based on formal verification and relative timing, to create and prove correct necessary constraints to support asynchronous design with traditional clocked CAD. These constraints support timing driven synthesis, place and route, and behavior and timing validation of fully asynchronous designs using traditional clocked CAD flows. This flow is demonstrated through a simple example pipeline in IBM's 65nm process showing the ability to retarget the design for improved power and performance.

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“…This was demonstrated in the Intel RAPPID project in which an asynchronous instruction length decoder for an x86 processor was designed using timed circuits. It was found to be three times faster while using half the power of the comparable synchronous design [17].…”

Section: Introductionmentioning

confidence: 96%

Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits

Nelson¹,

Myers²,

Yoneda³

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit timing information for optimization throughout the entire design process. In asynchronous circuits, correct operation requires that there are no hazards in the circuit implementation. Therefore, when designing an asynchronous circuit, each internal node and output of the circuit must be verified for hazard-freedom to ensure correct operation. Current verification algorithms for timed asynchronous circuits require an explicit state exploration often resulting in state explosion for even modest sized examples. The goal of this work is to abstract the behavior of internal nodes and utilize this information to make a conservative determination of hazard-freedom for each node in the circuit. Experimental results indicate that this approach is substantially more efficient than existing timing verification tools. These results also indicate that this method scales well for large examples. It is capable of analyzing circuits in less than a second that could not be previously analyzed. While this method is conservative in that some false hazards may be reported, our results indicate that the number of false hazards is small.

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An asynchronous instruction length decoder

Cited by 59 publications

References 21 publications

Radiation Hardening by Design of Asynchronous Logic for Hostile Environments

Radiation Hardening by Design of Asynchronous Logic for Hostile Environments

Characterization of Asynchronous Templates for Integration into Clocked CAD Flows

Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits

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