An asynchronous low-power 80C51 microcontroller

Gageldonk, H. van; Berkel, Kees van; Peeters, A.; Baumann, David; Gloor, D.; Stegmann, G.

doi:10.1109/async.1998.666497

Cited by 122 publications

(46 citation statements)

References 7 publications

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“…HC-based designs have been shown to have good energy usage characteristics [9] but poor performance [16]. Both of these characteristics can be attributed to the control-heavy nature of HCs.…”

Section: A Handshake Components and Synthesismentioning

confidence: 99%

Teak: A Token-Flow Implementation for the Balsa Language

Bardsley

Tarazona

Edwards

2009

2009 Ninth International Conference on Application of Concurrency to System Design

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Abstract-This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise handshake interleaving and enclosure by separating out control 'go' and 'done' signalling into separate channels rather than using different phases of the asynchronous handshake. This leads to circuits in which optimisation and control overhead mitigation can be carried out by merging/separating control and data channels and by introducing handshake-decoupling latches. This work aims to make Balsa descriptions implementable in the more widely used and understood higher performance token-based asynchronous circuit styles.

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Section: A Handshake Components and Synthesismentioning

confidence: 99%

Teak: A Token-Flow Implementation for the Balsa Language

Bardsley

Tarazona

Edwards

2009

2009 Ninth International Conference on Application of Concurrency to System Design

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“…Additionally, the asynchronous circuit has less emission of electro-magnetic noise (EMI) [9] feature because the asynchronous design methodologies do not employee globalized common and periodic control signal. These are reasons why [10]- [12] were introduced.…”

Section: Introductionmentioning

confidence: 99%

Implementation of an Asynchronous Micro-controlleron the Commercial FPGA

Shin¹,

Oh²,

Kwon³

et al. 2017

IJCTE

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Abstract-An asynchronous circuit design methodology has been introduced as a novelty approach to future digital system design. Nevertheless, in order to implement the asynchronous circuit, there are various limitations. Especially, for the implementation on a commercialized field programmable gate array (FPGA), the vendors and design tools mainly support only synchronous circuit design. In this paper, we propose design techniques for implementing the asynchronous circuit on the commercial FPGA using the provided design tool. Then, with the proposed design techniques, we designed an asynchronous micro-controller based onaTIMSP430 instruction set architecture (ISA).We observe that the asynchronous core consumes lower power than the synchronous one. In addition, the asynchronous core also shows much more durability under conditions of unstable power supplies compared to the synchronous counterpart.Index Terms-Asynchronous circuit, AFSM, bounded delay, FPGA.

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“…Actually, the demand of low-power electronic components in all embedded and miniaturized applications encourages companies to develop asynchronous versions of the existing time-triggered components, where a significant power consumption reduction can be achieved by decreasing the samplings and consequently the CPU utilization: about four times less power than its synchronous counterpart for the 80C51 microcontroller of Philips Semiconductors in [6] for example. An original and simple event-based PID control architecture was proposed in [7].…”

Section: Introductionmentioning

confidence: 99%