An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications

Abstract

Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for real-time power system simulators is needed. In this article, a prototype of this approach is presented, employing Field Programmable Gate Array (FPGA) platforms due to their reconfigurability that enables low-power, low-latency, and high-performance designs, as a first attempt towards an open source platform, compatible with the majority of hardware design suites. It comprises two major parts: (i) a user-oriented section, built in Matlab/Simulink; and (ii) a hardware-oriented section, written in Matlab and Very High Speed Integrated Circuit (VHSIC)-Hardware Description Language (VHDL) code. To verify its functionality, two test power networks were given in a schematic format, analyzed through Matlab code and turned into dedicated hardware simulators with the aid of the VHDL template. Then, simulation results from Simulink and the prototype were compared for error estimation. The results show the prototype's successful implementation with minimal resources utilization, high performance and low latency in the order of nanoseconds in Xilinx 6-and 7-series FPGAs, therefore proving its modularity and efficient use in many different scenarios, meeting low-latency/real-time requirements while enabling further smart grid research.

Comparison of Different Design Alternatives for Hardware-in-the-Loop of Power Converters

“…When designing digital circuits, the first step is to prepare a device architecture description by codifying the system's behavior, making it possible to standardize the design process. The models can be codified at Register Transfer Level (RTL) using HDL languages, such as VHDL [25,26] or Verilog [27,28]. However, the handcrafted HDL code needs remarkable design effort because it must specify the functionality at a low level of abstraction, where cycle-by-cycle behavior is entirely determined.…”

Design and Experimental Validation of Power Electric Vehicle Emulator for Testing Electric Vehicle Supply Equipment (EVSE) with Vehicle-to-Grid (V2G) Capability

“…In order to use this functionality, EVSE must be integrated into the building Energy Managment System (EMS), which will handle the charging or discharging according to the needs of the building [7,8]. Therefore, to ensure the proper behaviour of these new systems, the research of suitable test systems can establish the Smart Grid development [9,10].…”

Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA

“…HIL (hardware-in-the-loop) techniques are being increasingly used for testing and simulation of complex systems, such as power electronics [1][2][3][4] and mechanical elements [5][6][7][8]. These techniques consist in replacing an element of the real system with a model.…”