An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits

Farisi, Brahim Al; Bruneel, Karel; Cardoso, João M. P.; Stroobandt, Dirk

doi:10.7873/date.2013.174

Cited by 6 publications

(3 citation statements)

References 7 publications

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“…if they control the mode of a multi-mode circuit, however, finding these signals requires an analysis on a different scope and is not part of this paper. Multi-mode implementations using the TLUT tool flow are discussed in more detail in [15]. In [10], DCS implementations of different application types are explored.…”

Section: High-level Profilermentioning

confidence: 99%

Data path analysis for dynamic circuit specialisation

Davidson

Stroobandt

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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Abstract-Dynamic Circuit Specialisation (DCS) is a method that exploits the reconfigurability of modern FPGAs to allow the specialisation of FPGA circuits at run-time. Currently, it is only explored as part of Register-transfer level design. However, at the Register-transfer level (RTL), a large part of the design is already locked in. Therefore, maximally exploiting the opportunities of DCS could require a costly redesign. It would be interesting to already have insight in the opportunities for DCS from the higher abstraction level. Moreover, the general design trend in FPGA design is to work on higher abstraction levels and let tool(s) translate this higher level description to RTL. This paper presents the first profiler that, based on the high-level description of an application, estimates the benefits of an implementation using DCS. This allows a designer to determine much earlier in the design cycle whether or not DCS would be interesting. The highlevel profiling methodology was implemented and tested on a set of PID designs.

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Section: High-level Profilermentioning

confidence: 99%

Data path analysis for dynamic circuit specialisation

Davidson

Stroobandt

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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“…RESEARCH OVERWIEW Figure 1 shows an overview of the different tool flows developed in our research. Figure 1(a) shows the first tool flow we developed, in which the joint optimization happens in an extra step before placement [2]. In this step the different Lookup Table (LUT) circuits are merged into something called a Tunable circuit.…”

Section: Introductionmentioning

confidence: 99%

“…In the second tool flow, shown in Figure 1(b), the different modes are jointly optimized during placement [2]. This joint placement step tries to reduce the total wire length needed by TRoute.…”

Section: Introductionmentioning

confidence: 99%

Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits

Farisi

Heyse

Stroobandt

2014

2014 International Conference on Field-Programmable Technology (FPT)

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A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using dynamic partial reconfiguration of an FPGA, all the modes can be implemented on the same reconfigurable region, requiring only an area that can contain the biggest mode. This can save considerable chip area. Conventional dynamic partial reconfiguration techniques generate a configuration for every mode separately. As a result, to switch between modes the complete reconfigurable region is rewritten, which often leads to long reconfiguration times. In this paper we give an overview of research we conducted to reduce this overhead of dynamic partial reconfiguration for multi-mode circuits. In this research we explored several joint optimization strategies at different stages of the tool flow.

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Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

Farisi

Heyse

Bruneel

et al. 2014

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Using dynamic partial reconfiguration (DPR), several circuits can be time-multiplexed on the same FPGA region, saving considerable area compared to an implementation without DPR. However, the long reconfiguration time to switch between circuits remains a significant problem. In this work we show that it is possible to significantly reduce this overhead when the number of circuits is limited. We lower the DPR overhead by reducing the number of configuration bits that needs to be reconfigured. This is achieved by keeping a (predetermined) part of the configuration frames of the DPR region constant/static for all circuits and, consequentially, sharing this part of the configuration between all the circuits. We show that this can be done maintaining the possibility to implement completely unrelated circuits in the DPR region. An extension of the Pathfinder algorithm, called StaticRoute, is presented. It is able to route the nets of the different circuits simultaneously in such a way that the routing of the different circuits is the same in the static part and may only differ in the dynamic part. Our approach is evaluated on the architecture of a commercially available SRAM-based FPGA. We explore how the static part in the configuration memory is best chosen and investigate the associated impact on maximum operating clock frequency as the number of circuits increases. Our experiments show that it is possible to make 50 % of the routing configuration static and therefore reduce the routing reconfiguration time by 50 %, without a significant impact on maximum clock frequency of the circuits. This corresponds to a reduction of total reconfiguration time of 34 %

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An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits

Cited by 6 publications

References 7 publications

Data path analysis for dynamic circuit specialisation

Data path analysis for dynamic circuit specialisation

Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits

Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

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