An effective approach to detect logic soft errors in digital circuits based on GRAAL

Abstract

Due to the notable change of channel width, supply voltage; and clock frequency, CMOS IC technologies are rapidly approaching their ultimate limits. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable error rates and make further nanometer scaling increasingly difficult. The error detection scheme based on GRAAL architecture (Global Reliability Architecture Approach for Logic) combines latch-based design and time redundancy techniques to achieve high detection efficiency for temporary faults (timing faults, SEUs, and SETs) at low area, power and speed penalties. In this paper, we use a finite state machine (FSM) circuit as test vehicle to validate the error detection architecture. The experimental results validate the claimed high error detection efficiency.

A hybrid optimization approach to conformance testing of finite automata

“…The U-method is used in testing network protocols [4] and sequential circuits [23,24]. Test case should be as short as possible.…”

Logic masking for SET Mitigation Using Approximate Logic Circuits

“…Electrical masking is exploited by using larger transistors or nodal capacitances [1], [2]. Latch-window masking is exploited by using time redundancy based on latching data at different times [3], [4]. Finally, techniques based on logic masking are proposed in [5], [6], [7], [8] and [13].…”

A Co-Design Approach for SET Mitigation in Embedded Systems

“…Solutions to mitigate SET effects can be divided into hardware-based approaches and software-based approaches. Hardware-based approaches have been proposed at several abstraction levels, ranging from specialized cells, such as guard gates [2] or variations of Dual-Interlocked Storage Cell (DICE) [3], to combinational logic redundancy [4], [5], time redundancy [6], [7], and system level redundancy by using multiple processors, coprocessors or specialized system modules [8], [9]. These approaches usually introduce a severe penalty in area, performance and power consumption.…”