An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC

Lee, Seon-Young; Cho, Kyeongsoon

doi:10.1093/ietfec/e89-a.6.1736

Cited by 5 publications

(7 citation statements)

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“…Most deblocking filter designs focus on the data transportation and the filtering order instead of the kernel filter design [4]- [13]. However, all of them used the MBbased filtering orders, which are inefficient for the B8-level pipeline.…”

Section: Efficient Deblocking Filter For B8-based Processing Granularitymentioning

confidence: 99%

“…The synthesized gate count is about 8K at 162 MHz. As compared to the state-of-the-art designs where the gate count of logic circuit ranges between 7.5K to 24K [4]- [13], the cost of the proposed design is relatively low.…”

Section: The Proposed Architecture Of Deblocking Filtermentioning

confidence: 99%

“…Thirdly, to further reduce the bus bandwidth and the processing latency, we use a single-port SRAM as line buffer to store a frame-wide row of 4x4 blocks. Therefore, there are 20 alternatives among which 17 of them are MB-based [4]- [13] approaches and the other 3 are of B8based approaches. In summary, our design space exploration covers a total of 160 (2*4*20) combinations.…”

Section: Design Space Exploration Of the Video Pipementioning

confidence: 99%

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Design space exploration of an H.264/AVC-based video embedding transcoder using transaction level modeling

Peng

Chiang

2008

2008 IEEE International Conference on Multimedia and Expo

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In this paper, we perform the design space exploration for an H.264/AVC video embedding transcoder. Specifically, the design space is pruned for the sub-modules including inverse transform, inter and intra prediction, and deblocking filter with various microarchitecture designs, processing order, memory hierarchy, and granularity of synchronization. In addition, we propose an efficient deblocking filter suitable for 8x8 block pipeline. Compared to the traditional designs, our proposed deblocking filter reduces memory requirement, processing latency, and access frequency to the local memory. The synthesized logic gate count is only 8K using the 0.18 um technology with the maximum frequency of 162 MHz. For rapid exploration, all the design alternatives are simulated with higher level of abstraction using the transaction level modeling to explore 160 design combinations. Our simulation results provide an extensive tradeoff analysis among processing speed, cost, and utilization. Besides, the cost-normalized hardware utilization where the cost of each sub-module weights its associated utilization assists the system designers to keep a balance across different modules.Index Terms-Video embedding transcoder, design space exploration, transaction level modeling.

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Section: Efficient Deblocking Filter For B8-based Processing Granularitymentioning

confidence: 99%

Section: The Proposed Architecture Of Deblocking Filtermentioning

confidence: 99%

Section: Design Space Exploration Of the Video Pipementioning

confidence: 99%

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Design space exploration of an H.264/AVC-based video embedding transcoder using transaction level modeling

Peng

Chiang

2008

2008 IEEE International Conference on Multimedia and Expo

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“…In Fig. 1 deblocking filtering are based on a single filter unit for both horizontal and vertical filtering [1]. In order to increase the filtering performance, this paper proposes a novel deblocking filter architecture based on two identical filtering units, allowing simultaneous on-the-fly filtering of vertical and horizontal edges.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Architecture for Hardware Implementation of H.264/AVC Deblocking Filtering

Tobajas

Callicó

Perez

et al. 2008

2008 Digest of Technical Papers - International Conference on Consumer Electronics

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“…The reference software uses a straight forward approach to implementing the deblocking algorithms defined in [1]. A number of hardware solutions [4][5][6][7][8][9][10][11][12][13][14] have been proposed to improve the direct implementation of the software algorithm. Each of these approaches makes certain tradeoffs to improve performance.…”

Section: Introductionmentioning

confidence: 99%

A data traffic efficient H.264 deblocking IP

Hao¹,

Radetzki²

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a H.264 deblocking IP that minimizes the data traffic by avoiding repeated read and write operations of the same pixels with the help of local buffers and increased data locality through a functionally equivalent reordering of the deblocking process. The microarchitecture of the IP uses a sophisticated datapath and controller to pipeline the memory access and deblocking steps, leading to full utilization of resources and a minimal cycle count per macroblock. The IP has been prototyped on FPGA, achieving an operating frequency of >100 MHz, and it is capable of supporting 720p (1280x720) deblocking at frame rates up to 144 Hz (or higher resolution at lower rate). Its equivalent logic gate count, obtained by synthesis to ASIC technology, is 10.46k excluding SRAMs.

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An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC

Cited by 5 publications

References 0 publications

Design space exploration of an H.264/AVC-based video embedding transcoder using transaction level modeling

Design space exploration of an H.264/AVC-based video embedding transcoder using transaction level modeling

An Efficient Architecture for Hardware Implementation of H.264/AVC Deblocking Filtering

A data traffic efficient H.264 deblocking IP

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