An efficient hardware architecture design for H.264/AVC INTRA 4×4 algorithm

Abstract

In this work, we present architecture for real-time implementation of INTRA 4X4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4X4 is composed by intra prediction 4x4, integer transform 4x4, quantization 4x4, inverse integer transform 4x4, inverse quantization 4x4 .This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 160 MHz in an ALTERA Stratix II FPGA. This architecture can process one macroblock (MB) for 432 clock cycles. I.978-1-4244-3477-0/08/$25.00 ©2008 IEEE

Intra 4*4 Mode Architecture Design in H.264/AVC Intra Prediction

“…The results of synthesis indicate that in the Altera StratixIII EP3SL150F1152C2N FPGA platform, the consumption of logic elements and memory bits are 15415 and 28 KB respectively. The comparison of the performance with similar designs is shown in table 4 As can be seen from the table 4, the intra 4×4 computing speeds up by 9% and the frequency decreases by 6% than the 432 cycles in [6], with the increase of 5% logic elements consumptions and 70% memory bits. Since the architecture design of this paper is within the intra prediction module, as well as without the optimization of the cache units, it has a much larger memory bits than that in [6].…”

“…The comparison of the performance with similar designs is shown in table 4 As can be seen from the table 4, the intra 4×4 computing speeds up by 9% and the frequency decreases by 6% than the 432 cycles in [6], with the increase of 5% logic elements consumptions and 70% memory bits. Since the architecture design of this paper is within the intra prediction module, as well as without the optimization of the cache units, it has a much larger memory bits than that in [6]. Compared to the [7], both the computing speed and the hardware cost have greatly improved.…”

Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application

“…Since the H.264/AVC standardization, many research works have been devoted to developing several hardware approaches for the intra prediction module; among them, we can mention the designs proposed in [19,20]. With the emergence of the HEVC standard, efforts have been directed to adapt and ameliorate previous works to the new intra prediction algorithm.…”