Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application

Kammoun, Manel; Atitallah, Ahmed Ben; Atitallah, Rabıe Ben; Nouri, Mohammad

doi:10.1002/cta.2308

Cited by 18 publications

(11 citation statements)

References 15 publications

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“…The methodology is ideal for incorporating into an FPGA or ASIC design flow, which has suggested a methodology that integrates standard building blocks into safe compound gates. Register Transfer Level is a level of abstraction of the effective framework used by M.Kammoun et al [11] in order to evaluate the various methods of hardware and software in terms of energy consumption and execution time, especially for video coding systems, as large data processing is required. A FPGA (Field Programmable Gate Arrays) based on Xilinx Zynq was used for this search.…”

Section: Abstraction Levels Classificationmentioning

confidence: 99%

A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

et al. 2021

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Simulating systems on a chip (SoC) even before starting its productivity makes it possible to validate the correct functioning of the systems, also avoiding the manufacture of defective chips. However, low-level design and system complexity makes verification and simulation more complicated and time consuming. The classification of the different levels of abstraction from lowest to highest generally depends on the estimation accuracy of the system performance and the speed of simulation. The RTL (Register Transfer Level) abstraction level allows efficient description at gate level with good precision. Therefore, RTL program are slowly simulated. Simulation speed usually depends on the size of the platform used, which is not the case for transaction level modeling (TLM) to achieve simulation speed based on the exchange of transactions between system modules. This work aims to give a detailed description of the different levels of abstraction with the main advantages, and disadvantages on the performances estimation side such as, energy consumption, precision, and speed. Furthermore, an overview of the most adequate memory architectures and interconnection networks, to aim the most suitable virtual platforms of simulation for SoC.

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Section: Abstraction Levels Classificationmentioning

confidence: 99%

A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

et al. 2021

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“…11. On the other hand, the work presented in [33] proved that the AXI4-Lite bus performances are limited since it provides a sequential transfer of only 32-bit data. This generates a huge communication time and makes the transfer a bit slow.…”

Section: Sw/hw Solutions Exploration and Performance Evaluationmentioning

confidence: 99%

HW/SW Architecture Exploration for an Efficient Implementation of the Secure Hash Algorithm SHA-256

Kammoun

Elleuchi

Abid

et al. 2021

JCOMSS

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Hash functions are used in the majority of security protocol to guarantee the integrity and the authenticity. Among the most important hash functions is the SHA-2 family, which offers higher security and solved the insecurity problems of other popular algorithms as MD5, SHA-1 and SHA-0. However, theses security algorithms are characterized by a certain amount of complex computations and consume a lot of energy. In order to reduce the power consumption as required in the majority of embedded applications, a solution consists to exploit a critical part on accelerator (hardware). In this paper, we propose a hardware/software exploration for the implementation of SHA256 algorithm. For hardware design, two principal design methods are proceeded: Low level synthesis (LLS) and high level synthesis (HLS). The exploration allows the evaluation of performances in term of area, throughput and power consumption. The synthesis results under Zynq 7000 based-FPGA reflect a significant improvement of about 80% and 15% respectively in FPGA resources and throughput for the LLS hardware design compared to HLS solution. For better efficiency, hardware IPs are deduced and implemented within HW/SW system on chip. The experiments are performed using Xilinx ZC 702-based platform. The HW/SW LLS design records a gain of 10% to 25% in term of execution time and 73% in term of power consumption.

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“…It is used to support all transform matrix sizes (from 4 × 4 to 32 × 32 TUs). The IDCT equations defined in the HEVC test model decoder reference software version 10 (HM10) [20] present many multiplications by constants, which is very costly in terms of area and power consumption [21]. To reduce the computational complexity and increase the performance of the proposed architecture, these multiplications are replaced by shift and addition operations.…”

Section: The 2d-idct/idst Hardware Designmentioning

confidence: 99%

“…However, the HW blocks are created and customized using the Xilinx platform studio. From Figure 11, we can see that the communication between the ARM Cortex A9 processor and the IQ/IT hardware block is carried out using the AXI4-stream interface [21,26] which is specially designed for maximum bandwidth access to the on-chip memory and DDR memory of the PS. This mode of transfer supports unlimited data burst sizes and provides point-to-point streaming data without using any addresses.…”

Section: Sw/hw Performance Evaluationmentioning

confidence: 99%

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Atitallah¹,

Kammoun²,

Atitallah³

2020

Turk J Elec Eng & Comp Sci

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This paper presents an optimized hardware architecture of the inverse quantization and the inverse transform (IQ/IT) for a high-efficiency video coding (HEVC) decoder. Our highly parallel and pipelined architecture was designed to support all HEVC Transform Unit (TU) sizes: 4 × 4, 8 × 8, 16 × 16 , and 32 × 32. The IQ/IT was described in the VHSIC hardware description language and synthesized to Xilinx XC7Z020 field-programmable gate array (FPGA) and to TSMC 180 nm standard-cell library. The throughput of the hardware architecture reached in the worst case a processing rate of up to 1080 p at 33 fps at 146 MHz and 1080 p at 25 fps at 110 MHz when mapped to FPGA and standardcells, respectively. The validation of our architecture was conducted on the ZC702 platform using a Software/Hardware (SW/HW) enviro nment in order to evaluate different implementation methods (SW and SW/HW) in terms of power consumption and run-time. The experimental results demonstrate that the SW/HW accelerations were enhanced by more than 70% in terms of the run-time speed relative to the SW solution. Besides, the power consumption of the SW/HW designs was reduced by nearly 60% compared with the SW case.

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Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application

Cited by 18 publications

References 15 publications

A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

HW/SW Architecture Exploration for an Efficient Implementation of the Secure Hash Algorithm SHA-256

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

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