An efficient implementation of the 1D DCT using FPGA technology

El-Banna, H. H.; El-Fattah, A.A.; Fakhr, W.

doi:10.1109/icm.2003.237829

Cited by 13 publications

(3 citation statements)

References 9 publications

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“…, 7. This particular definition of the DCT is adopted in [38,39,40], having been considered to derive the well-known Loeffler DCT algorithm [16]. Notice that √ 2·c4 = 1; therefore the DC component…”

Section: Nmentioning

confidence: 99%

Efficient Computation of the 8-point DCT via Summation by Parts

Coelho

Cintra

Dimitrov

2017

J Sign Process Syst

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This paper introduces a new fast algorithm for the 8-point discrete cosine transform (DCT) based on the summation-by-parts formula. The proposed method converts the DCT matrix into an alternative transformation matrix that can be decomposed into sparse matrices of low multiplicative complexity. The method is capable of scaled and exact DCT computation and its associated fast algorithm achieves the theoretical minimal multiplicative complexity for the 8-point DCT. Depending on the nature of the input signal simplifications can be introduced and the overall complexity of the proposed algorithm can be further reduced. Several types of input signal are analyzed: arbitrary, null mean, accumulated, and null mean/accumulated signal. The proposed tool has potential application in harmonic detection, image enhancement, and feature extraction, where input signal DC level is discarded and/or the signal is required to be integrated.Comment: 13 pages, 4 figures, 2 table

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Section: Nmentioning

confidence: 99%

Efficient Computation of the 8-point DCT via Summation by Parts

Coelho

Cintra

Dimitrov

2017

J Sign Process Syst

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“…1D DCT blocks along row and column implement 2D DCT. In the proposed architecture of 1D Fast Discrete Cosine Transform, it has been implemented by Distributed Arithmetic [16], [19] in Fig. 8.…”

Section: E Discrete Cosine Transformmentioning

confidence: 99%

A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays

Sinha

Sarkar

Acharyya

et al. 2013

SIGARCH Comput. Archit. News

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Development of modern integrated circuit technologies makes it feasible to develop cheaper, faster and smaller special purpose signal processing function circuits. Digital Signal processing functions are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively smaller utilization factor or lower speed compared to ASIC. Field Programmable DSP Array (FPDA) is the proposed DSP dedicated device, redolent to FPGA, but with basic fixed common modules (CMs) (like adders, subtractors, multipliers, scaling units, shifters) instead of CLBs. This paper introduces the development of reconfigurable system architecture with a focus on FPDA that integrates different DSP functions like DFT, FFT, DCT, FIR, IIR, and DWT etc. The switching between DSP functions is occurred by reconfiguring the interconnection between CMs. Validation of the proposed architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility, parallelism and scalability.

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“…1D DCT blocks along row and column implement 2D DCT. In the proposed architecture of 1D Fast Discrete Cosine Transform, it has been implemented by Distributed Arithmetic [17], [18] in Figure 9. DCT constant coefficient for N = 16 can be represented as: The matrix has been decomposed into even and odd subscript matrices.…”

Section: Discrete Cosine Transformmentioning

confidence: 99%