An efficient inductance modeling for on-chip interconnects

Abstract

In this paper, we present an efficient yet accurate inductance extraction methodology. We first show that without loss of accuracy, the extraction problem of n traces can be reduced to a number of one-trace and two-trace subproblems. We then solve one-trace and two-trace subproblems via a tablebased approach. The table-based inductance model has been integrated with a statistically-based RC model generation [l] to generate RLC models for on-chip interconnects. Application examples show that our method is efficient enough to be used during iterative procedures of interconnect simulation and layout optimization.[. INTRODUCTIONIt has been shown for years that interconnect delay and crosstalk have become bottle necks in determining circuit performance. In order to simulate and optimize on-chip interconnects, the parasitic parameters (resistance, capacitance and inductance) need to be extracted from the interconnect geometry. This extraction nnust be accurate as a correlation with "final" verification engjnes is needed for design convergence. The extraction must also be efficient, because it may be performed dozens of times on the full-chip level and thousands of times on critical nets. Clearly, numerical extraction is hard to support during iterative procedures of simulation and optimization.Accurate and efficient extractions for resistance and capacitance have been achieved recently. For example, a 2.5D capacitance extraction methodology was shipped with Cadence Silicon Ensemble 5.0 product[2], and a fast generation of statistically-based worst-case RC models was implemented and used at Hewlett-Packard [I]. Both used the tablebased approach, which is suitable for iterative simulation and opt&ization purposes. Due to increasingly wider and longer wire traces, faster clock frequencies and shorter rising times, inductance effects of on-chip interconnects no longer can be ignored. However, no1 inductance extraction methodology, which is accurate and efficient for iterative simulation and optimization purposes, has been presented.In this paper, we describe an efficient and accurate methodology to extract inductance under the PEEC model. In section II, we validate two foundations which allow us to reduce the problem size of inductance extraction without loss of accu-1. Lei He is a PhD candidate at UCLA, Computer Science Dept..He worked with HP labs during 1998 summer and fall. Address comments to helei@cs.ucla.edu and nchang@hpI.hp.com racy. In section 111, we propose a table-based inductance extraction methodology based on the two foundations. In section IV, we present two applications of the inductaince extraction methodology: (i) to derive the effective (loop) inductance for a coplanar-waveguide; (ii) to be integrated with the statistically-based RC model generation in [l] to generate RLC models for onchip interconnects. We also use the RLC model to optimize bus structures. Section V concludes this paper. Foundations for Inductance Extraction A. PreliminariesThere are multiple metal layers in a VLSI technology. We assu...

Modeling and Application of Multi-Port TSV Networks in 3-D IC

“…Taking inductance as an example, the inductance matrix L for two TSV conductors can be expressed as (15) where L 11 is the partial self-inductance of a single TSV and L p is the loop inductance of a TSV pair. Fundamentally, in a multi-conductor system, the self inductance of one conductor is solely decided by the conductor itself, while the mutual inductance of two conductors is solely decided by the two conductors [4], [6]. The full partial inductance matrix for a general N-TSV network can be expressed as…”

“…Computational methods with filament approximation were widely developed [4]- [6] based on the concepts of those partial elements. In some situations, however, when integralequation based PEEC methods cannot obtain partial elements easily while the loop or pair-based elements among filaments are available through other methods, a numerical scheme as Algorithm 1 can be used to obtain circuit models for these complex structures.…”

“…The partial element equivalent circuit (PEEC) model [4], [5] has been widely used in inductance and capacitance extraction tools for planar on-chip traces. In a typical PEEC model, the reference has to be defined at infinity for partial inductance and capacitance [5], [6]. However, when applying the PEEC model to TSV networks, the complex 3-D metal-insulatorsemiconductor (MIS) structure of TSV and the lossy silicon substrate make it difficult to find the partial inductance and partial capacitance efficiently.…”

Expression of Concern: On the accuracy of return path assumption for loop inductance extraction for 0.1 μm technology and beyond

“…In the extraction, the difficulty comes from identifying the actual current return paths that define the current loop. The most common assumption, regardless of the frequency of interest, is to restrict the current return paths to the closest power or ground lines [2], [3], [5], [6]. This assumption is widely accepted because it localizes the extraction window and simplifies the inductance extraction at the design stage.…”

“…Since inductance is a physical property of a current loop, inductance extraction method based on a priori knowledge of the current return path is called loop inductance. Loop inductance based methods have been used in analytical inductance model proposed in [2], table-based inductance modeling in [3], and frequency dependent inductance and resistance extraction in [4].…”