An Efficient List Decoder Architecture for Polar Codes

Abstract

Long polar codes can achieve the symmetric capacity of arbitrary binary-input discrete memoryless channels under a low complexity successive cancelation (SC) decoding algorithm. However, for polar codes with short and moderate code length, the decoding performance of the SC algorithm is inferior. The cyclic redundancy check (CRC) aided successive cancelation list (SCL) decoding algorithm has better error performance than the SC algorithm for short or moderate polar codes. In this paper, we propose an efficient list decoder architecture for the CRC aided SCL algorithm, based on both algorithmic reformulations and architectural techniques. In particular, an area efficient message memory architecture is proposed to reduce the area of the proposed decoder architecture. An efficient path pruning unit suitable for large list size is also proposed. For a polar code of length 1024 and rate 1 2 , when list size L = 2 and 4, the proposed list decoder architecture is implemented under a TSMC 90nm CMOS technology. Compared with the list decoders in the literature, our decoder achieves 1.24 to 1.83 times hardware efficiency.

A Complexity Reduction Method for Successive Cancellation List Decoding

“…Table III gives the implementation results for state-of-the-art sorters and the sorter designs explained in the previous section. We consider the simplified bubble sorter (SBS) [26], radix-2L sorter [5], MVF [20] and simplified odd-even sorter (OES) [27] for comparison. From the results in Tables II and III, one can directly observe that the crossbar complexities are significantly higher than those of the sorters.…”

“…One of the sorter architectures we employ in our designs is the radix-2L sorter [5], [23]. Other sorting methods we consider are the bitonic sorter proposed in [24] [20]. MVF is a bitonic sorter without the final sorting stages, so that it extracts L paths with the smallest path metrics out of 2L candidate paths without any ordering.…”

An Asymmetric Adaptive SCL Decoder Hardware for Ultra-Low-Error-Rate Polar Codes

“…As shown in Fig. 4, the FER curves of N = 1024, K = [1/8, 7/8] Polar codes with quantization bits = [6,8,12] are almost the same under SC decoding. Accordingly, 6-bits or 8-bits quantization is sufficient for SC decoders.…”

A Flip-Syndrome-List Polar Decoder Architecture for Ultra-Low-Latency Communications

“…• Do not split upon the most reliable (good) bits [12], [13]. 3) Reduce the latency of list pruning • Adopt bitonic sort [14] for efficient pruning.…”

“…According to our measurement under typical code lengths, the main source of latency is now incurred by the general nodes whose constituent code rates are between 2 B and B−2 B . Motivated by [7]- [11], and thanks to the recent advances in efficient list pruning [14], [15], we find it profitable to further improve parallelism for ultra-low-latency applications. Our contributions are summarized below: 1) We propose to fully parallelize the processing of R1/SPC nodes via multi-bit hard estimation and flipping at intermediate stages.…”