An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains

Rau, Jiann-Chyi; Lin, Ching-Hsiu; Chang, Jun-Yi

doi:10.1109/ats.2004.23

Cited by 5 publications

(1 citation statement)

References 7 publications

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“…These methods, however, concentrate on single scan chain optimization. Layout based multiple scan chain optimization methods can be found in [5], [10]. However, in [5], the test power dissipation in the circuit is not considered, while in [10], scan chain improvement is somewhat less than our proposed method.…”

Section: Introductionmentioning

confidence: 96%

Genetic Algorithm based Scan Chain Optimization and Test Power Reduction using Physical Information

Paul

Mukhopadhyay

Gupta

2006

TENCON 2006 - 2006 IEEE Region 10 Conference

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In this paper, we consider genetic algorithm to optimize the scan chain length of a given circuit and minimize the power dissipation during testing. For scan chain optimization, we use layout information so as to have a more accurate modeling of scan chain lengths. At the same time, we also try to minimize the test power by reducing switching activity in the scan flip-flops during scan test operation. The scan chain is partitioned into a specified number of sub chains in order to further minimize the scan chain length, routing overhead and test power. Experimental results have been reported on ISCAS-89 benchmark circuits.

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Section: Introductionmentioning

confidence: 96%