An efficient methodology for building macromodels of IC fabrication processes

Low, Kevin

doi:10.1109/43.44510

Cited by 55 publications

(22 citation statements)

References 12 publications

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“…circuit modeling, and will assume, that the transformation φ can be non-linear and perhaps implicit, as implemented with a statistical macro-model of parameter variability [1], [2], [3], [4] or a statistical fabrication process simulator [5], [6].…”

Section: Circuit Model For Statistical Design Centeringmentioning

confidence: 99%

Remarks on Statistical Design Centering

Opalski¹

2011

International Journal of Electronics and Telecommunications

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Abstract-The paper overviews optimization based statistical design centering techniques for analog circuits. Emphasis is placed on dependence between formulation of quality indices, problem formulation, and computational complexity of design centering algorithms, executed in single-or multiple-processor environments. For characterization of solution techniques a standard CMOS op-amp design case and a simplified computational complexity analysis are used.

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Section: Circuit Model For Statistical Design Centeringmentioning

confidence: 99%

Remarks on Statistical Design Centering

Opalski¹

2011

International Journal of Electronics and Telecommunications

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“…The concept of desirability functions used in conjunction with experimental designs was described in 1965 by Harrington EC [2]. Coupling both concepts of numerical design of experiments and desirability functions to optimize a physical system was surprisingly used in very few papers essentially devoted to semiconductor technology [3][4][5][6][7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Optimizing an electrochemical deposition process by use of design of computer experiments

Rabiot¹,

Caire²,

Nguyen³

et al. 1998

Analusis

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Abstract.A response surface methodology only based in this case on computer experiments was used in conjunction with the desirability concept to optimize a priori an electrodeposition process designed for production of gold-tin alloy bumps on a 4 inches wafer. The efficiency of the method was used to achieve at a cheap cost with a small number of computer experiments the technical specifications required in term of metal deposit thickness uniformity.

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“…There are several traditional techniques, such as principal component analysis [9], variable screening [10] or projection pursuit [11], which aim to reduce the computation cost of response surface modeling. In this subsection, we compare PROBE with these traditional techniques and highlight their differences.…”

Section: Comparison With Traditional Techniquesmentioning

confidence: 99%

“…Variable screening is another traditional approach for reducing the response surface modeling cost [10]. Given a circuit performance f, variable screening applies fractional factorial experimental design and tries to identify a subset (hopefully small) of the random process parameters that have much greater influence on f than the others.…”

Section: Low-dimensional Spacementioning

confidence: 99%

“…The additional coordinate rotation offers more flexibility in filtering out insignificant components, thereby achieving better modeling accuracy and/or cheaper modeling cost. From this point of view, the proposed PROBE can be considered as a generalized variable screening which is an extension of the traditional variable screening in [10]. Projection pursuit [11] tries to approximate the unknown high-dimensional nonlinear function by the sum of several smooth low-dimensional functions.…”

Section: Low-dimensional Spacementioning

confidence: 99%

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Projection-based performance modeling for inter/intra-die variations

Li¹,

Le²,

Pileggi³

et al.

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

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Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations. Fitting such models requires significantly more simulation samples and solving much larger linear equations. In this paper, we propose a novel projection-based extraction approach, PROBE, to efficiently create quadratic response surface models and capture both interdie and intra-die variations with affordable computation cost. PROBE applies a novel projection scheme to reduce the response surface modeling cost (i.e., both the required number of samples and the linear equation size) and make the modeling problem tractable even for large problem sizes. In addition, a new implicit power iteration algorithm is developed to find the optimal projection space and solve for the unknown model coefficients. Several circuit examples from both digital and analog circuit modeling applications demonstrate that PROBE can generate accurate response surface models while achieving up to 12x speedup compared with the traditional methods. IntroductionAs IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations, particularly due to sub-wavelength photolithography [1]- [2]. The increasing fluctuations in manufacturing process have introduced unavoidable and significant uncertainty in circuit performance. Hence, modeling and analyzing these random process variations to ensure manufacturability and improve yield has been identified as a top priority for today's IC design problems.In order to address this process variation problem, response surface models [3] are utilized to capture the circuit performance variations caused by manufacturing fluctuations. The objective of response surface modeling is to approximate the circuit performance (e.g., delay, gain) as a polynomial (e.g., linear or quadratic) function of variational process parameters (e.g., V TH , T OX ). These models are extensively applied in many applications such as statistical timing analysis [1], analog mismatch analysisMost of the previous response surface models, e.g., [1], utilize linear approximations, which are efficient and accurate when process variations are sufficiently small. However, two recent changes in advanced IC technologies suggest a need to revisit this assumption. Firstly, process variations are becoming relatively larger. As reported in [1], the gate length variation can reach ±35% in nano-scale technologies. This, in turn, implies the importance of applying high-order (e.g., quadratic) response surface models to guarantee high approximation accuracy [3], [6], [7]. Applying nonlinear response surface models is especially important for analog circuits, since many analog performances (e.g., offset voltage) can be strongly nonlinear in the presence of large-scale variations.Secondly, but most importantly, intra-die variations (i.e., mismatches) are becoming increasingly important [2], especially for analog ...

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An efficient methodology for building macromodels of IC fabrication processes

Cited by 55 publications

References 12 publications

Remarks on Statistical Design Centering

Remarks on Statistical Design Centering

Optimizing an electrochemical deposition process by use of design of computer experiments

Projection-based performance modeling for inter/intra-die variations

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