Projection-based performance modeling for inter/intra-die variations

Abstract

Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations. Fitting such models requires significantly more simulation samples and solving much larger linear equations. In this paper, we propose a novel projection-based extraction approach, PROBE, to efficiently create quadratic response surface models and capture both interdie and intra-die variations with affordable computation cost. PROBE applies a novel projection scheme to reduce the response surface modeling cost (i.e., both the required number of samples and the linear equation size) and make the modeling problem tractable even for large problem sizes. In addition, a new implicit power iteration algorithm is developed to find the optimal projection space and solve for the unknown model coefficients. Several circuit examples from both digital and analog circuit modeling applications demonstrate that PROBE can generate accurate response surface models while achieving up to 12x speedup compared with the traditional methods. IntroductionAs IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations, particularly due to sub-wavelength photolithography [1]- [2]. The increasing fluctuations in manufacturing process have introduced unavoidable and significant uncertainty in circuit performance. Hence, modeling and analyzing these random process variations to ensure manufacturability and improve yield has been identified as a top priority for today's IC design problems.In order to address this process variation problem, response surface models [3] are utilized to capture the circuit performance variations caused by manufacturing fluctuations. The objective of response surface modeling is to approximate the circuit performance (e.g., delay, gain) as a polynomial (e.g., linear or quadratic) function of variational process parameters (e.g., V TH , T OX ). These models are extensively applied in many applications such as statistical timing analysis [1], analog mismatch analysisMost of the previous response surface models, e.g., [1], utilize linear approximations, which are efficient and accurate when process variations are sufficiently small. However, two recent changes in advanced IC technologies suggest a need to revisit this assumption. Firstly, process variations are becoming relatively larger. As reported in [1], the gate length variation can reach ±35% in nano-scale technologies. This, in turn, implies the importance of applying high-order (e.g., quadratic) response surface models to guarantee high approximation accuracy [3], [6], [7]. Applying nonlinear response surface models is especially important for analog circuits, since many analog performances (e.g., offset voltage) can be strongly nonlinear in the presence of large-scale variations.Secondly, but most importantly, intra-die variations (i.e., mismatches) are becoming increasingly important [2], especially for analog ...