An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU

Arakawa, Fumio; Okada, Takashi; Hayashi, Tomoichi; Nishii, O.; Hattori, Toshihiro

doi:10.1016/j.micpro.2009.02.004

Cited by 3 publications

(3 citation statements)

References 3 publications

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“…This method is particularly advantageous for fine-grain HWAs with low latency. An example is the SuperH processor [5] where the FPU is part of the CPU pipeline and shares the CPU register file.…”

Section: Background and Related Workmentioning

confidence: 99%

Interfacing hardware accelerators to a time-division multiplexing network-on-chip

Pezzarossa

Sørensen

Schoeberl

et al. 2015

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &Amp; International Symposium on System-on-Chip (SoC)

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This paper addresses the integration of stateless hardware accelerators into time-predictable multi-core platforms based on time-division multiplexing networks-on-chip. Stateless hardware accelerators, like floating-point units, are typically attached as co-processors to individual processors in the platform. Our design takes a different approach and connects the hardware accelerators to the network-on-chip in the same way as processor cores. Each processor that uses a hardware accelerator is assigned a virtual channel for sending instructions to the hardware accelerator and a virtual channel for receiving results. This allows a stateless and possibly pipelined hardware accelerator to be shared in an interleaved fashion without any form of reservation, and this opens for interesting area-performance trade-offs. The design is developed with a focus on time-predictability, areaefficiency, and FPGA implementation. The design evaluation is carried out using the open source T-CREST multi-core platform implemented on an Altera Cyclone IV FPGA. The size of the proposed design, including a floating-point accelerator, is about two-thirds of a processor.

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Section: Background and Related Workmentioning

confidence: 99%

Interfacing hardware accelerators to a time-division multiplexing network-on-chip

Pezzarossa

Sørensen

Schoeberl

et al. 2015

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &Amp; International Symposium on System-on-Chip (SoC)

View full text Add to dashboard Cite

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“…19. For example, the chip presented in [39] achieves similar energy efficiency, but has substantially lower area efficiency, while the chip in [36] reaches similar area efficiency but has lower energy efficiency.…”

Section: Energy and Area Efficiencymentioning

confidence: 99%

Power and Area Minimization for Multidimensional Signal Processing

Marković

Nikolić

Brodersen

2007

IEEE J. Solid-State Circuits

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Abstract-Sensitivity-based methodology is applied to optimization of performance, power and area across several levels of design abstraction for a complex wireless baseband signal processing algorithm. The design framework is based on a unified, block-based graphical description of the algorithm to avoid design re-entry in various phases of chip development. The use of architectural techniques for minimization of power and area for complex signal processing algorithms is demonstrated using this framework. As a proof of concept, an ASIC realization of the MIMO baseband signal processing for a multi-antenna WLAN is described. The chip implements a 4 4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1 GOPS/mW (12-bit add equivalent) in just 3.5 mm 2 in a standard 90 nm CMOS process. The computational throughput of 70 GOPS is implemented with 0.5 M cells at a 100 MHz clock and 385 mV supply, dissipating 34 mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250 Mb/s over 16 sub-carriers.

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“…These works all focus on core pipeline architecture and circuit-level power reduction. Arakawa et al integrate a floating-point unit (FPU) into a general-purpose processing core and optimize the FPU pipeline [12]. Sohn et al design the first chip supporting the vertex shader model for mobile devices in the literature [14]; however, only fixed-point datapaths are supported, which cannot satisfy the realistic graphic effects of complicated scenes as desktop GPUs do.…”

Section: Introductionmentioning

confidence: 99%

An 8.6 mW 25 Mvertices/s 400-MFLOPS 800-MOPS 8.91 mm$^{2}$ Multimedia Stream Processor Core for Mobile Applications

Chien¹,

Tsao²,

Chang³

et al. 2008

IEEE J. Solid-State Circuits

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For the demands of mobile multimedia applications, a stream processor core is designed with 8.91 mm 2 area in 0.18 m CMOS technology at 50 MHz. Several techniques and architectures are proposed to achieve high performance with low power consumption. First of all, an optimized core pipeline is designed with 2-issue VLIW architecture to achieve the processing capability of 400 MFLOPS or 800 MOPS. In addition, adaptive multi-thread scheme can increase the performance by increasing hardware utilization, and the proposed configurable memory array architecture can reduce off-chip memory accessing frequency by caching both input data and output results. Furthermore, for graphics applications, a geometry-content-aware technique called early-rejection-after-transformation is proposed to remove redundant operations for invisible triangles. As for video applications, the proposed video accelerating instruction set can support motion estimation for video coding. Experimental results show that 86% power reduction and more than ten times speedup of the VLIW architecture can be achieved with the proposed techniques to provide the processing speed of 25 Mvertices/s and power consumption of 8.6 mW. Moreover, CIF (352 288) 30 fps video encoding with the search range of {H[ 24,24), V[ 16,16]} is also supported by the proposed stream processor. By supporting both video and graphics functions, this highly efficient, high performance, and low power processor core is applicable to multimedia mobile devices.

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An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU

Cited by 3 publications

References 3 publications

Interfacing hardware accelerators to a time-division multiplexing network-on-chip

Interfacing hardware accelerators to a time-division multiplexing network-on-chip

Power and Area Minimization for Multidimensional Signal Processing

An 8.6 mW 25 Mvertices/s 400-MFLOPS 800-MOPS 8.91 mm$^{2}$ Multimedia Stream Processor Core for Mobile Applications

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