Power and Area Minimization for Multidimensional Signal Processing

Abstract

Abstract-Sensitivity-based methodology is applied to optimization of performance, power and area across several levels of design abstraction for a complex wireless baseband signal processing algorithm. The design framework is based on a unified, block-based graphical description of the algorithm to avoid design re-entry in various phases of chip development. The use of architectural techniques for minimization of power and area for complex signal processing algorithms is demonstrated using this framework. As a proof of concept, an ASIC realization of the MIMO baseband signal processing for a multi-antenna WLAN is described. The chip implements a 4 4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1 GOPS/mW (12-bit add equivalent) in just 3.5 mm 2 in a standard 90 nm CMOS process. The computational throughput of 70 GOPS is implemented with 0.5 M cells at a 100 MHz clock and 385 mV supply, dissipating 34 mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250 Mb/s over 16 sub-carriers.

An Automated Fixed-Point Optimization Tool in MATLAB XSG/SynDSP Environment

“…This approach made feasible the optimization of a 1 million gate chip. Using automated FPGA mapping from XSG, the designer was able to immediately verify all functional modes of the optimized design in hardware before physical chip synthesis [31], giving designers much higher confidence in the functionality of the fabricated chip. These chips also demonstrate hierarchical extension of the 1/square-root block illustrated in Figure 12, and [31] has more details about the design.…”

A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS

“…4. Sensitivity-based optimization has been demonstrated in the architecture and circuit levels [6]. In this work, we further extend the optimization up to algorithm level.…”

“…Synplify DSP [7] is used to evaluate various hardware architectures and to automate HDL generation. Wordlength and architecture are optimized with in-house tools [5] [6]. Critical modules are refined to enhance the circuit performance.…”

Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

“…quad-core processors) but can do little for extending the battery life and cooling due to their compact form factor. Hence, mobile applications require circuits to be extremely energy efficient and at the system level, this requires careful and joint selection of solutions not only at the algorithm and architecture levels but also at the circuits level [1]. Hence, circuits should also be thought within the context of its target application and designed by considering the application-specific properties.…”