An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic

Zhang, Yimeng; Okamura, Leona; Yoshihara, Tsutomu

doi:10.1587/transele.e94.c.605

Cited by 8 publications

(9 citation statements)

References 9 publications

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“…The power dissipation analysis method of pNBL is similar with that applied on PBL in Ref [12]. To apply this analysis, some assumptions as preconditions are required.…”

Section: Energy Dissipationmentioning

confidence: 99%

“…Interface between static CMOS is a pNBL buffer, with which input DC signals can be transferred to sinwave-like signals, and setup/hold time of generated signals can also satisfy the requirement of pNBL. Interface between pNBL and static CMOS is the same with that described in Ref [12], which can be recognized as a 1-bit A/D converter. This data A/D converter samples data when output is in the peak values, and therefore delay caused by it is small comparing with cycle time of power clock.…”

Section: Design Pe With Pnblmentioning

confidence: 99%

“…[1][2][3][4][5][6][7] can hardly work correctly. To satisfy the high operation frequency requirement, a charge recovery logic family named boost logic [9][10][11][12] is proposed. Boost logics use two-phase nonoverlap clock signal as power clock to drive circuits, and operation frequency can reach as high as Gigahertz while the power dissipation can keep in a low level comparing with the conventional static CMOS.…”

Section: Introductionmentioning

confidence: 99%

“…In Section II, operation of pseudo-NMOS boost logic is discussed, and comparison between pNBL and the previous boost logics (i.e. PBL [12] and EBL [10]) is described. The structure of Processing Engine is discussed in Section III.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Energy Efficient Processing Engine in LDPC Application with High-Speed Charge Recovery Logic

Zhang¹,

Huang²,

Wang³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 µm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

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“…The power dissipation analysis method of pNBL is similar with that applied on PBL in Ref [12]. To apply this analysis, some assumptions as preconditions are required.…”

Section: Energy Dissipationmentioning

confidence: 99%

Section: Design Pe With Pnblmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Energy Efficient Processing Engine in LDPC Application with High-Speed Charge Recovery Logic

Zhang¹,

Huang²,

Wang³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

Self Cite

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show abstract

“…In numerous presented literatures [1], [2], [3], charge recovery logics have demonstrated that their power dissipation performance has great potential. Charge recovery logic can achieve high power dissipation performance because circuit energies are conserved rather than dissipated as heat.…”

Section: Introductionmentioning

confidence: 99%

A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic

Zhang

Huang

Wang

et al. 2011

IEEE Asian Solid-State Circuits Conference 2011

Self Cite

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This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven, low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18µm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1pJ/cycle when working at the frequency of 403MHz, which is only 36% of PE with conventional static CMOS gates. The measurement results shows that the test chip can work as high as 609MHz with the energy dissipation of 2.1pJ/cycle.

show abstract

Design of 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counter

Mei

Wang

2011

2011 9th IEEE International Conference on ASIC

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An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic

Cited by 8 publications

References 9 publications

Energy Efficient Processing Engine in LDPC Application with High-Speed Charge Recovery Logic

Energy Efficient Processing Engine in LDPC Application with High-Speed Charge Recovery Logic

A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic

Design of 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counter

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