In this paper, we propose an ultra high-throughput LDPC decoder SOC to fulfill the requirement of IEEE 802.15.3c standard. By implementing a macro-layer fully parallel architecture, our proposed decoder takes only 4 clock cycles to finish one layered decoding iteration. Interconnection complexity problem introduced by highparallel decoding is nicely solved by proposed reusable message permutation networks utilizing the features of code PCM. Critical path is shortened by applying frame-level pipeline decoding. A 65nm CMOS chip is fabricated to verify the proposed architecture. Measured at 1.2V, 400MHz and 10 iterations the proposed decoder achieves a data throughput 6.72Gb/s and consumes a power 537.6mW with an energy efficiency 8.0 pJ/bitͼiter.

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A four phase switched polarity charge pump using O.13JLm triple well CMOS technology is presented. The architecture takes advantage of the threshold voltage cancellation scheme in the conventional four phase Dickson charge pump. With the body control technique, the body effect is eliminated. The charge transfer unit is shared in positive and negative operation, which makes the design more compact. Simulation results show that the proposed 5-stage charge pump can reach +8.22V/-8.05V (ideal: +9V/-9V) with 10% of total capacitance as estimated parastics, and the output indicates good linearity with respect to the increase of stages.